Method of and apparatus for designing circuit block layout in in

Details Method of and apparatus for designing circuit block layout in in Method of and apparatus for designing circuit block layout in in

1990-06-26

1994-05-03

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

053093712

ABSTRACT:
There are provided a method of and an apparatus for designing a circuit block layout in an integrated circuit wherein minimization of a total wiring length among the circuit blocks and compaction of the circuit blocks are automatically achieved upon automatically laying out the circuit blocks and determining wiring among those circuit blocks, by initially laying out the circuit blocks using a spring model of a mass point system where circuit blocks with no size are coupled through springs, configuring at least partial circuit blocks as circles to re-lay out the circuit blocks such that there is eliminated any overlapping among the circuit blocks, compacting the external shape of an assembly of the circuit blocks by matching the external shape with the frame of a die and altering the shape of each circuit block from the circle to an actual shape.

REFERENCES:
patent: 4500963 (1985-02-01), Smith et al.
patent: 4593362 (1986-06-01), Bergeron et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4615011 (1986-09-01), Linsker
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4754408 (1988-06-01), Carpenter et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4858143 (1989-08-01), Fourier
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Madarres et al.
patent: 5046017 (1991-09-01), Yuyama et al.
"Partitioning and Placement Technique for CMOS Gate Arrays" by Odawara et al., IEEE Trans. on Computer-Aided-Design, CAD-6, No. 3, May 1987, pp. 355-363.
"Compaction Based Custom LSI Layout Design Method" by Ishikawa et al., IEEE ICCAD-85, Nov. 18-Nov. 21, 1985, pp. 343-345.
"A Block Interconnection Algorithm for Hierarchical Layout System" by Fukui et al., IEEE Trans. Computer-Aided Design, vol. CAD 6, No. 3, May 1987, pp. 383-390.
"An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI Floor-Plan" by Tsukiyama et al., IEEE ISCC, May 5-7, 1986, pp. 321-324.
"A Block Placement Procedure Using a Force Model", Hidetoshi Onodera and Keikichi Tamaru, Papers Journal of Japan Electronics and Information Communication Society vol. J 72-A No. 1 pp. 105-113, Jan. 1989.
Nikkei Electronics, Jul. 28, 1986, (No. 400) pp. 289-298, "CAD System With Fully Automatic Layout of Standard Cell LSI".
"Step by Step Placement Strategies for Building Block Layout", 1989 IEEE International Symposium on Circuits and Systems, vol. 2 of 3, pp. 921-926.
"CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design", IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 1, Jan. 1985, pp. 12-22.
"ALSO: A System for Chip Floorplan Design", Integration, The VLSI Journal, Jul. 1988, No. 2, pp. 127-146.
"A Forced Directed Component Placement Procedure for Printed Circuit Boards", IEEE Transactions on Circuit and Systems, vol. CAS-26, No. 6, Jun. 1979, pp. 377-388.
"Data in the Meeting for the Research of the Design Automation in the Society of Information Transaction", 18-3, Sep. 1983.

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