Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-10-17
2006-10-17
Paladini, Albert W. (Department: 2125)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
07124070
ABSTRACT:
For deriving an RTL description through several steps from a behavioral description, a behavioral synthesis device outputs an associated relation between intermediate level descriptions subsequent to the respective steps and intermediate level descriptions prior to the respective steps. A model extracting device extracts a model capable of expressing a control structure based on a finite state machine and an update of a signal from the behavioral description, each of the intermediate level descriptions, and the RTL description, as a model corresponding to those descriptions. A signal value function extracting device extracts signal value functions from the model. A function equivalence comparing device checks the equivalence between signal value functions prior and subsequent to the steps of the behavioral synthesis device.
REFERENCES:
patent: 6470482 (2002-10-01), Rostoker et al.
patent: 6587590 (2003-07-01), Pan
patent: 6691301 (2004-02-01), Bowen
patent: 6718522 (2004-04-01), McBride et al.
patent: 6813201 (2004-11-01), Zarrineh et al.
patent: 6910200 (2005-06-01), Aubel et al.
P. Ashar et al., “Verification of Scheduling in the Presence of Loops Using Uninterrupted Symbolic Simulation”, International Conference on Computer Design, (1999), pp. 458-466 with Abstract.
N. Mansouri et al., “Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs”, Formal Methods of System Design, vol. 16, (2000), pp. 59-91 with Abstract.
NEC Corporation
Paladini Albert W.
Sughrue & Mion, PLLC
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