Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1997-05-01
2001-12-11
Bella, Matthew C. (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S151000, C382S147000, C382S149000, C382S174000
Reexamination Certificate
active
06330354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to testing of circuit devices, and more specifically, to analyzing image data to find defects on a device.
2. Background Art
Advances in integrated circuits have enhanced the ability to integrate increasingly more circuits on a single chip. As the circuit complexity on a chip increases, so does the need to thoroughly test the chip for defects caused through manufacture processing, misalignment of circuit elements, improper dicing, environmental factors, such as dirt, heat, etc. At the present, the common method of testing semiconductor chips is to visually inspect the chip for defects, which are found through color and size gradients. Many of the defects to date can only be found by manual examination, allowing for fatigue and human error. That is, examinations have been done manually because of the intricacies and complexities involved in thoroughly testing the various layers of a semiconductor computer chip, and in the cases of expensive and important equipment the percent of error should be minimal.
Automated systems have been developed for the testing of larger devices with a few layers, such as the ceramic chip. Because the circuitry has only a few, accessible layers, the devices are easily tested against a reference pattern, and categorized as falling within the required standards or not. Examples of automated systems testing with a reference pattern include: U.S. Pat. No. 5,172,420 “Method for Monitoring the Dimensions and Other Aspects Linewidth Thickness and Discoloration of Specular Patterns” (issued Dec. 15, 1992 to Ray et al. and assigned to AT&T Bell Laboratories); U.S. Pat. No. 5,146,509 “Method of Inspecting Defects in Circuit Pattern and System for Carrying Out the Method” (issued Sep. 8, 1992 to Hara et al. and assigned to Hitachi, Ltd.); U.S. Pat. No. 5,103,304 “High-Resolution Vision System for Part Inspection” (issued Apr. 7, 1992 to Turcheck, Jr. et al. and assigned to FMC Corp.); U.S. Pat. No. 5,023,917 “Method and Apparatus for Pattern Inspection” (issued Jun. 11, 1991 to Bose et al. and assigned to AT&T Bell Lab.); U.S. Pat. No. 4,648,053 “High Speed Optical Inspection System” (issued Mar. 3, 1987 to Fridge and assigned to Kollmorgen Technologies, Corp.); U.S. Pat. No. 4,587,617 “Image Inspection System for Defect Detection” (issued May 6, 1986 to Barker et al. and assigned to Cambridge Instruments Ltd.); and U.S. Pat. No. 5,475,766 “Pattern Inspection Apparatus With Ocrner Rounding of Reference Pattern Data” (issued Dec. 12, 1995 to Tsuchiya et al. and assigned to Kabushiki Kaisha Toshiba).
Although the aforementioned patents automatically test circuit boards with a reference pattern, having one set reference pattern for testing smaller devices, such as semiconductor chips, would result in many false positives (i.e., results that indicate a chip is defected, when in fact the chip still falls within an acceptable range of operability). False positives would most likely occur because the above-mentioned patents can only handle a couple of layers, repetitive pattern sequences, or specific shape/size measurements of the chip components. Furthermore, since there are numerous amounts of defects that could occur on any level of a multi-layer device, pattern testing that is created for a few exposed layers is not sophisticated enough to recognize the subtle defects, or even the larger defects on the lower levels of the multi-layered device that may be disastrous to the operability of the device. Finally, none of the patents address testing devices with solder pads, which are vital in communicating with the outside world.
Accordingly, a need has developed in the art for a method to automatically test an image for defects in a small, multi-layered device having a solder pad, such as a semiconductor computer chip.
SUMMARY OF THE INVENTION
It is thus an advantage of the present invention to provide a method to test small, multi-layered devices with a minimal amount of false positive results.
It is yet another advantage of the present invention to provide a method to successfully test devices having solder pads.
The foregoing and other advantages of the invention are realized by a method that provides a device template image(s), a theoretical image created from data from an averaged set of real images that are obtained from known good devices, for comparison to an image of a device to be tested after the solder pad data is segmented. Parameter values of the device to be tested are recorded and compared to the parameter values of the device template, forming a difference image. The difference image and the solder pad data are then run through a series of tests, wherein the device is determined defective or not defective.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 3916439 (1975-10-01), Lloyd et al.
patent: 4319845 (1982-03-01), Shuji
patent: 4441124 (1984-04-01), Heebner et al.
patent: 4587617 (1986-05-01), Barker et al.
patent: 4589140 (1986-05-01), Bishop et al.
patent: 4633504 (1986-12-01), Wihl
patent: 4648053 (1987-03-01), Fridge
patent: 4688939 (1987-08-01), Ray
patent: 4740708 (1988-04-01), Batchelder
patent: 4809341 (1989-02-01), Matsui et al.
patent: 4845764 (1989-07-01), Ueda et al.
patent: 4851902 (1989-07-01), Tezuka et al.
patent: 4860371 (1989-08-01), Matsuyama et al.
patent: 5003615 (1991-03-01), Seitz
patent: 5012502 (1991-04-01), Battin et al.
patent: 5023917 (1991-06-01), Bose et al.
patent: 5054097 (1991-10-01), Flinois et al.
patent: 5058178 (1991-10-01), Ray
patent: 5093797 (1992-03-01), Yotsuya et al.
patent: 5103304 (1992-04-01), Turcheck, Jr. et al.
patent: 5146509 (1992-09-01), Hara et al.
patent: 5163128 (1992-11-01), Straayer
patent: 5172420 (1992-12-01), Ray et al.
patent: 5311598 (1994-05-01), Bose et al.
patent: 5351201 (1994-09-01), Harshbarger, Jr. et al.
patent: 5440396 (1995-08-01), Markus et al.
patent: 5455870 (1995-10-01), Sepai et al.
patent: 5475766 (1995-12-01), Tsuchiya et al.
patent: 5548326 (1996-08-01), Michael
patent: 5640199 (1997-06-01), Garakani et al.
patent: 5640200 (1997-06-01), Michael
patent: 5692070 (1997-11-01), Kobayashi
patent: 5719951 (1998-02-01), Shackleton et al.
patent: 5760829 (1998-06-01), Sussmeier
patent: 5850466 (1998-12-01), Schott
IBM/ vol. 27/No. 10A/ Mar. 1985/Dynamic Chip Pad Volume Analysis Tool.
William M. Silver, Congnex Corp. “Golden Template Comparison” The Journal of Machine Perception, vol. 7, No. 11, p. 20-24 Oct. 1990.*
William M. Silver “Golden Template Comparison”, Sensors the journal of machine perception, Oct. 1990, vol. 7 No. 11, Oct. 15, 1999.
Companion Pierre M.
Moody, III Karl K.
Wilson Brenda M.
Bella Matthew C.
Chawan Sheela
International Business Machines - Corporation
Leas James M.
LandOfFree
Method of analyzing visual inspection image data to find... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of analyzing visual inspection image data to find..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of analyzing visual inspection image data to find... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2572579