Method of altering a non-volatile semiconductor memory device

Details Method of altering a non-volatile semiconductor memory device Method of altering a non-volatile semiconductor memory device

1993-04-22

1995-04-18

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 365900, 365218, G11C 1604

Patent

active

054084296

ABSTRACT:
A method for writing data to a selected EEPROM memory cell and erasing data in a selected EEPROM memory cell. During writing of the EEPROM memory cell, a tunnel effect is used to draw charges from the charge injection layer of a memory transistor into the drain. A negative voltage lower than ground potential is applied to the control gate of the selected memory cell and the presence or absence of the tunnel effect is controlled by the level of voltage applied to the drain of the selected memory cell. Other memory cells which are not being written with data are maintained free of the tunnel effect by applying a voltage higher than the gate voltage of the selected memory cell, and lower than the threshold voltage of the control gate to the non-selected memory cell with respect to its drain connection. During erasing of a selected memory cell, the power supply voltage for the memory is applied to the control gate of the selected memory cell and the drain and source are grounded. The control gate of the non-selected memory cell is placed at a ground potential, inhibiting erasing of the non-selected cell.

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"Flash EEPROM Cell Scaling Based on Tunnel Oxide Thinning Limitations" K. Yoshikawa et al. 1991 VLSI Symposium Technology, pp. 77-80.

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