Method of adjusting threshold voltage subsequent to fabrication

Details Method of adjusting threshold voltage subsequent to fabrication Method of adjusting threshold voltage subsequent to fabrication

1986-04-07

1987-10-20

Roy, Upendra

Fishing, trapping, and vermin destroying

357 91, 437 29, 437 44, 437 45, 148DIG84, H01L 21265, H01L 21322

Patent

active

047014229

ABSTRACT:
A method of adjusting the threshold voltages of field effect transistors fabricated on a III-V compound semi-insulating wafer includes the steps of measuring the threshold voltages of the transistor, directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value, and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implantation. The III-V compound semi-insulating wafer may be GaAs. The ion beam may be supplied as protons accelerated to approximately 320 KeV with a concentration of between approximately 10.sup.11 and 10.sup.13 protons/cm.sup.-2. The wafer may be annealed at a temperature from approximately 100.degree. C. to approximately 300.degree. C. (for approximately one half hour at 300.degree. C. The field effect transistors may be depletion mode or enhancement mode field effect transistors. In addition, the field effect transistors may initially be depletion mode field effect transistors, but the intensity and duration of the directed ion beam may be made sufficient to convert the transistors into enhancement mode transistors.

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