Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-20
2003-03-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S189090
Reexamination Certificate
active
06535431
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories.
BACKGROUND OF THE INVENTION
In a NORed non-volatile memory, e.g., of the EEPROM type, the matrix of elementary cells is organized by the memory word, i.e., by the byte, in accordance with a known circuit diagram shown in FIG.
1
.
FIG. 2
shows to an enlarged scale the layout of a portion of the non-volatile memory of the EEPROM type.
Each byte forms a memory word and comprises a series of at least eight floating gate transistors, each connected in series to a respective selection transistor (bit switch) on a common bit line of the cell matrix.
Each floating gate transistor has a control gate capacitively coupled to the floating gate, and the control gates of the eight memory cells making up the byte are connected in parallel with one another by a common polysilicon connection. These control gates are also connected to a metallization line CG through a byte switch.
The gates of the byte switch and the 8 bit switches (more generally, all the switches on the same word line) are connected in parallel with one another by a polysilicon connection.
The erase operation is typically performed by the byte, by addressing the m-th word line (WL), corresponding to the m-th matrix row, and the n-th control gate (CG), corresponding to the n-th byte column.
The byte switch is operated by applying an elevated voltage (e.g., of 16V) to the m-th word line WL, so that an erase voltage can be transferred which is supplied on an n-th metallization line CG to the control gate of the desired byte transistors. In this way, electrons are injected into the floating gate, by a phenomenon known as Fowler-Nordheim tunnelling, to raise the threshold voltage for each bit.
The writing of individual bits, within a byte, is effected by addressing the respective word line WL (which may be biased to 16V, for example, with all the other word lines being at a ground potential), and applying a write voltage Vpp to a node BL k. The node is allowed to float according to whether the bit is to be written or held in an erased state. The write voltage applied to the node BL k is transferred to the drain terminal of the floating gate transistor (i.e., to the memory cell) by means of the selection transistor or bit switch, thereby depleting the floating gate of electrons and lowering the threshold voltage of the memory cell.
The cell content is read by biasing the m-th word line WL of the selected matrix row to a suitable voltage, addressing the n-th column CG (as biased to an intermediate voltage to the threshold values of the written and the erased cells), and applying a read voltage to the node BL k. By measuring the current drawn through the bit line, the charged state of the floating gate, drawing a larger or lesser amount of current according to whether it is negative or positive, can be found.
The write/erase voltage is generated and adjusted within the memory device itself. Thus, a single adjustment for both operations is desirable, as shown in the block diagram of FIG.
3
.
A variation &Dgr;Vt occurs in the threshold voltage with respect to a value Vt
U−V
, which corresponds to absence of charge in the floating gate, according to either of two states: erased or written. This voltage variation is tied to the injection current F-N, given by the following relation:
Δ
V
t
=
1
C
∫
0
T
P
I
FN
(
E
ox
(
t
)
)
ⅆ
t
(
1
)
The current F-N is, in turn, dependent on the electric field across the tunnel oxide of the memory cell; this electric field is given approximately by relation (2) below.
&LeftBracketingBar;
E
ox
(
t
)
&RightBracketingBar;
~
&LeftBracketingBar;
V
FG
(
t
)
-
V
D
&RightBracketingBar;
T
ox
(
2
)
where,
V
FG
(
t
)=&agr;
G
V
G
(
t
)+&agr;
S
V
S+&agr;
D
V
D
(
t
)+&agr;
B
V
B
+Q
FG
(
t
)/
Ctot
(3)
and &agr;
G
, &agr;
S
, &agr;
D
, &agr;
B
are the gate, source, drain, and body capacitive coupling coefficients, respectively.
These values are given as &agr;i=Ci/Ctot, where Ci is the capacitance between the floating gate and the corresponding i-th region, and Ctot=&Sgr;i Ci, as shown schematically in FIG.
4
.
During the erasing phase, the one voltage other than zero is the voltage applied to the control gate, and during the writing phase, the one non-zero voltage is that applied to the drain terminal. Thus (neglecting the floating gate variation in charged state), it is:
|
E
E
ox|∝&agr;
G
·V
PP
(
CG
)
and
|
E
W
ox
|∝(1−&agr;
D
)·
V
PP
(
D
)
Since relation &agr;
G
≈1−&agr;
D
is true (it being &agr;
S
, &agr;
B
<<1), it can be stated that:
|
E
E
ox|≈|E
W
ox
| if
Vpp
(
CG
)=
Vpp
(
D
).
In the most advanced of semiconductor integrated memory device fabrication processes, the doping of the polysilicon layer that forms the memory cell floating gate cannot be a heavy one, because CVD depositions with in situ doping are typically used and the equipment has limitations as regards control of the deposition process and the throughput phenomenon. In fact, the heavier the doping, the slower becomes the deposition, which obviously affects fabrication costs.
In addition, increasing the floating gate doping, such as by using known ion implantation techniques, is impracticable because it would affect the quality of the tunnel oxide significantly, also on account of the doping profile unavoidably exhibiting ion “tails” which would extend to the thin oxide and the substrate.
With too light a floating gate doping, a voltage loss may be incurred due to the floating gate depletion phenomenon during the erasing phase (Vcg=Vpp>>0), which would reflect in a lower effective electric field across the tunnel oxide than during the writing phase, and accordingly, in a threshold variation |&Dgr;Vt
E
|<|&Dgr;Vt
W
|.
It will be appreciated that this effect is highly undesirable, because the difference in the threshold voltage of a virgin cell, being used as a reference cell in sense amplifiers, and the corresponding voltage at the two logic states is not the same. In other words, the voltage Vt
E
does not split the total threshold variation.
In order to achieve a sufficient threshold variation of the erased cells compared to the virgin cell, the program voltage Vpp could be increased; however, this would not solve the problem of making the two different threshold voltages of the cell symmetrical, and moreover, would bring about writing conditions which are more stressing than is strictly necessary.
In fact, an injection of electrons from the floating gate into the substrate is specially critical to the thin oxide due to the peculiar nature of the polysilicon/dielectric interface. Furthermore, a possible generation of charges, following deflection of the bands near the N+/Psub junction and known as band-to-band tunnelling, can impair the device reliability.
Another problem is that the bit switch is to ensure lockout of the non-addressed memory cells on the same bit line during the reading phase, and is additionally used for transferring the program voltage Vpp to the cell drain during the writing phase.
To meet this requirement, it could be considered of increasing the threshold voltage Vt of the bit switch, such as by means of a dedicated LVS implant. But this would involve increased manufacturing costs because an additional mask would become necessary in the fabrication process flow.
SUMMARY OF THE INVENTION
Embodiments of this invention provide a method of adjusting the erase/program voltage in non-volatile memories, such that the two variations in the cell threshold voltage can be rendered symmetrical, thereby overcoming the aforementioned drawbacks of the prior art. In adjusting the erase/program voltage, a double adjustment is performed, whereby the program voltage can be higher during the erasing phase than during the writing phase.
Theref
Gomiero Enrico
Pio Federico
Zuliani Paola
de Guzman Dennis M.
Jorgenson Lisa K.
Le Vu A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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