Method of address distribution time reduction for high speed...

Details Method of address distribution time reduction for high speed... Method of address distribution time reduction for high speed...

2006-09-26

2006-09-26

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080

Reexamination Certificate

active

07113443

ABSTRACT:
An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

REFERENCES:
patent: 5894448 (1999-04-01), Amano et al.
patent: 6587391 (2003-07-01), Jung et al.

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