Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2001-06-06
2002-08-27
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C257S530000
Reexamination Certificate
active
06440781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a no-cost technique for adding bias independent aluminum bridged anti-fuse trim to a Tungsten plug process for fabricating integrated circuit structures.
2. Discussion of the Related Art
Zener zap diode anti-fuses, which depend upon bias direction to create the anti-fuse mechanism, are typically applied to integrated circuit fabrication processes that utilize interconnects of aluminum, aluminum alloy only, or an aluminum alloy with a barrier metal. An overview of Zener zap diode anti-fuse trim is presented by D. T. Comer, “Zener Zap Anti-Fuse Trim in VLSI Circuits”, VLSI Design, 1996, Vol. 5, No.1, pp. 89-100.
However, when Tungsten interconnect processes are used, the aluminum melt and flow mechanisms that Zener zap diodes rely upon are blocked. The blocking feature is the Tungsten plug itself.
Thus, there is a need for a bias-independent anti-fuse mechanism utilizable in a Tungsten plug process.
SUMMARY OF THE INVENTION
The present invention provides a three terminal integrated circuit device structure that relies upon the formation of an anti-fuse through the silicon substrate. This is accomplished by the melting and flowing of an aluminum alloy through the silicon to create a permanent conduction path. The use of an oversized contact permits the Tungsten plug to be eliminated from the anti-fuse structure, restoring the aluminum/aluminum alloy conduction path and allowing the aluminum/aluminum alloy melt and flow mechanism to be used with a Tungsten plug process. The design allows for a high resistance off state before trim and a low resistance state after trim. The technique is not dependant upon polarity, as is the case with Zener zap diodes.
The elimination of the Tungsten from the plug in the anti-fuse structure could be accomplished with a separate mask and etch step, but that would require extra processing and added cost. The present invention requires no additional processing.
As used in this document, the term “oversized contact” is defined as a contact where the width of the contact is greater than two times the Tungsten deposition thickness. Clearly for proper Tungsten plugs to be formed, this dimension must be less than two times the Tungsten thickness for the plug to fill properly without a center void. When the contact width is greater than two times the Tungsten thickness, the Tungsten etchback will penetrate the seam area and, if the width is large enough, the Tungsten will be removed from the contact bottom in the same manner that it is removed from the open area on the wafer.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which sets forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 4569120 (1986-02-01), Stacy et al.
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patent: 5679974 (1997-10-01), Shinriki et al.
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patent: 6016001 (2000-01-01), Sanchez et al.
patent: 6251710 (2001-06-01), Radens et al.
Donald T. Comer, “Zener Zap Anti-Fuse Trim in VLSI Circuits”, VLSI Design, 1996, vol. 5, No. 1, pp. 89-100.
Coppock William M.
Dark Charles
National Semiconductor Corporation
Pert Evan
Sherry Michael
Stallman & Pollock LLP
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