Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2001-02-28
2002-09-24
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C216S041000, C216S079000, C438S719000, C438S725000
Reexamination Certificate
active
06455333
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to small high density semiconductor devices. More particularly, the present invention relates to photoresist etching methods in the fabrication of semiconductor devices. Even more particularly, the present invention relates to stabilizing the a deep ultraviolet photoresist (hereinafter “resist”) etch rate for a gate critical dimension (hereinafter “CD”) of a semiconductor device.
BACKGROUND OF THE INVENTION
Currently, the need for high performance devices and low manufacturing cost has driven the semiconductor industry to higher density and smaller devices. In order to achieve the high density, the gate length of less than 100 nm is required. To cost-effectively achieve such gate lengths using current lithographic techniques is difficult, prompting the development of alternative methods. One such method of achieving smaller final CDs comprises lateral eroding of only a DUV resist before etching the gate material. This etch process involves several parameters (e.g., chemistry, system design, ion density, system pressure). Ion density is a function of applied power while the system pressure affects the mean free path of the ions. System pressures typically range from 0.4 mTorr to 50 mTorr while etch rates typically range from 600 Å/min to 2000 Å/min.
1
This method has been shown to be effective in minimizing the gate length to not less than 75 nm in a device; however, this DUV resist etch rate is found to be unstable and results in poor CD control. Due to cost concerns, the related art methods may involve seasoning a chamber with used polysilicon-only test wafers or resist-only coated wafers. This related art seasoning method provides only low and erratic resist etch rates which produces inconsistently etched layers, especially with respect to resist layers, in product wafers. Thus, wide spread etch rates lead to the related art problem of etch rate inconsistency. Therefore, a need exists for a method of stabilizing the DUV resist etch rate for a gate CD.
1
Peter Van Zant, Microchip Fabrication—A Practical Guide to Semiconductor Processing 3
rd
Ed., pp. 268-269 (1997).
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of stabilizing the DUV resist etch rate for a gate CD of ≦75 &mgr;m. More specifically, the present invention provides a method for stabilizing lateral erosion rate of the DUV resist by utilizing the directly proportionate relationship between the lateral erosion rate and a vertical etch rate:
R
L
=kR
V
,
where R
L
is the lateral erosion rate (i.e., trim rate) of the resist, R
V
is the vertical resist etch rate, and k is, therefore, a constant defined by the ratio of the trim rate to the vertical resist etch rate for any given set of photoresist and etchant combinations and conditions. Since measuring the lateral erosion is difficult, the present invention method provides better control of the DUV resist etch rate by measuring the vertical etch rate component. The present invention method involves a unique conditioning (i.e., seasoning) procedure using a distinct formulation in a decoupled plasma source (DPS) polysilicon etch chamber which results in consistent and stable DUV resist etch rates. The present invention seasoning is applied before processing of the wafer lot for providing better control of the gate CD targeting, and thereby possibly eliminating a “first wafer” effect.
In general, the present invention method of stabilizing a resist etch rate for at least one product wafer having at least one gate, comprises: (a) conditioning an etch chamber with a volatilized polymeric material, and thereby reducing etch chamber wall effects on an etchant; (b) providing a pilot wafer; (c) etching the pilot wafer in the etch chamber using the etchant, in accordance with a given etching technique; (d) verifying an optimum etch chamber conditioning, and if the optimum etch chamber conditioning is acceptable, proceeding to step (e), otherwise reconditioning the etch chamber by returning to step (a); (e) providing the at least one product wafer; and (f) etching the at least one product wafer in the etch chamber using the etchant, in accordance with the given etching technique.
REFERENCES:
patent: 6121155 (2000-09-01), Yang et al.
patent: 6270929 (2001-08-01), Lyons et al.
patent: 6271154 (2001-08-01), Shen et al.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Powell William A.
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