Method of accurate simulation of logic circuits

Details Method of accurate simulation of logic circuits Method of accurate simulation of logic circuits

1998-02-12

2002-10-29

Frejd, Russell (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S018000, C716S030000, C716S030000

Reexamination Certificate

active

06473725

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the simulation of logic circuits by means of a standardized language, such as VHDL or Verilog.
2. Discussion of the Related Art
VHDL, for example, is a high level language enabling a designer to define a complete logic circuit by a functional description. The description produced by the designer can be synthesizable or simulatable.
The synthesizable description is meant, through an appropriate software processing, to synthesize the circuit, that is, generate a definition of the elements that constitute the circuit (a netlist) which is directly exploitable by placement and routing tools for fabricating the corresponding integrated circuit.
During a synthesis step, the synthesizable description is decomposed into elementary logic functions implementable by elementary logic gates.
A simulatable description is meant to be processed by a logic simulator for generating, in particular, timing diagrams more or less accurately representing the logic evolution of the signals which will exist in a real circuit, this in order to check the proper operation of the circuit before effectively manufacturing it.
A simulatable description could include a synthesizable description only. The simulation would then provide the purely logic behavior of the circuit, which is however insufficient since the real elements of the circuit introduce signal delays which are not taken into account by a synthesizable description. These delays are likely to cause malfunctions of the real circuit whereas the pure logic behavior of the circuit is correct.
To detect these malfunctions, a simulatable description includes additional parameters to take delays into account.
A preliminary step in a simulation generally consists in converting a synthesizable description into a simulatable description by an automated processing. The synthesizable description is decomposed into elementary logic functions which are finally replaced with predefined models corresponding to elementary logic gates.
FIG. 1
schematically shows a general model of a logic gate. The model includes, in the general case, several inputs IN
1
to IN
n
and one output OUT connected to a capacitive load C. In this model, a logic table supplies the logic state of output OUT according to the logic states of the inputs (including output OUT itself for a flip-flop). Further, a description of the behavior in time defines the reaction delay of the output according to each input. More specifically, the model stores at least one delay tp per input and, if a change of state of one of inputs IN
i
should cause a transition on output OUT, the model generates this transition after the delay tp
i
associated with input IN
i
.
The simulated signals are purely logic, that is, they only take states “0” and “1”.
Hereafter, for clarity, a single-input model is considered, more specifically an inverter model. The following lines of VHDL partially represent an example of a simplified inverter model:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity IV is
generic(
IN_fall_OUT_rise : Time : = 0.094 ns;
IN_rise_OUT_fall : Time : = 0.087 ns;
);
port(
OUT:out STD_ULOGIC;
IN: in STD_ULOGIC
);
end IV;
Architecture naive Of IV Is
Begin
Process(IN)
Variable delay : Time;
Begin
if(IN= ‘1’) Then
delay := IN_rise_out_fall
else
delay := IN_fall_OUT_rise;
end if;
OUT <= !IN After delay ;
End
End naive;
The lines between “entity IV is” and “end IV” define the input IN and the output OUT of the inverter, as well as the delay parameters. There are here two delay parameters. Parameter IN_fall_OUT_rise defines the delay of a rising edge of signal OUT with respect to a falling edge of signal IN, and parameter IN_rise_OUT_fall defines the delay of a falling edge of output OUT with respect to a rising edge of input IN. Two parameters are thus available for a single input, which provides a good accuracy of the results of the simulation.
The lines between “Architecture naive Of IV Is” and “End naive” define the behavior of the inverter. Procedure “Process(IN)” is executed once for each change of state of input signal IN. Thus, as soon as signal IN changes state, it is checked whether its state is “1”. If such is the case, a variable “delay” is assigned with parameter IN_rise_OUT_fall. Otherwise, variable “delay” is assigned with the second parameter IN_fall_OUT_rise. Then, output signal OUT receives the complement of input signal IN when the time contained in variable “delay” expires.
The numerical values of the parameters indicated in the above example are default values depending on the used technology. One of the problems in simulation lies in the refining of the default parameters according to the real structure of the entire circuit.
FIG. 2
illustrates the calculation of a delay in the case of an inverter. Signals IN
R
and OUT
R
correspond to the real input and output signals of the inverter. Signals IN
S
and OUT
S
are simulated signals associated with real signals IN
R
and OUT
R
.
At time t
0
, signal IN
R
starts a rising transition shown, for simplicity, by a straight segment Isl. The rising transition of signal IN
R
causes a reaction of the inverter after a certain delay which depends on the technology used and on the slope Isl of the transition of input signal IN
R
. Thus, real output signal OUT
R
only starts a falling transition at a delayed time t
2
. The slope Osl of this falling transition depends on the capacitive load C of the line to which the inverter output is connected, but also on slope Isl of the transition of input signal IN
R
.
Simulated signals IN
S
and OUT
S
take only one or the other of logic states “0” and “1”, and therefore cannot reflect the slopes of the transitions. Thus, it is assumed that the state of simulated input signal IN
S
switches from “0” to “1” at a time t
1
when the rising transition of real signal IN
R
reaches a predetermined threshold. Similarly, it is assumed that the state of simulated output signal OUT
S
switches from “1” to “0” at a time t
3
when the falling transition of real signal OUT
R
reaches a predetermined threshold. In the example shown, the switching thresholds correspond to 50% of the high logic level, for both the rising transitions and the falling transitions of the real signals. It is also usual to use a 40% threshold for rising transitions and a 60% threshold for falling transitions.
Delay tp is the duration separating the times t
1
and t
3
where the transitions of real signals IN
R
and OUT
R
cross the switching thresholds, that is, the duration which separates the transitions of simulated signals IN
S
and OUT
S
.
As mentioned above, slope Osl of the output transition is a function of slope Isl of the input transition and of the capacitive load C to be controlled by the gate's output. As appears in
FIG. 2
, delay tp depends on slope Osl of the output transition and is thus also a function of slope Isl of the input transition and of load C. To summarize, tp=fd(C, Isl) and Osl=fs(C, Isl), where fd and fs are the two above-mentioned functions.
In the general case of a model with several inputs:
tp
i
=fd
i
(
C, Isl
i
)
and
Osl
i
=fs
i
(
C, Isl
i
),
where index i designates the input to which the delay and slope values are associated.
Currently, to perform an accurate simulation, the layout of the final circuit is first designed, which enables a relatively accurate calculation of the capacitive loads of the various lines interconnecting the logic elements. Further, the sizes of the transistors and the technology used determine the capacitances of the inputs of the logic elements, which add to the line capacitances.
When the capacitive loads have been calculated in this manner, a so-called back-annotation of the models is performed, which consists in replacing the default delays by values calculated before the simulation from the capacitive loads found.
In the general case, the output of a first model A with several inputs is connected to an input of

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