Method of accurate prediction of electrostatic discharge...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C361S091100, C257S355000

Reexamination Certificate

active

07987085

ABSTRACT:
The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.

REFERENCES:
patent: 6700164 (2004-03-01), Brennan et al.
patent: 7205613 (2007-04-01), Fjelstad et al.
patent: 2004/0239346 (2004-12-01), Iyer et al.
patent: 2004/0243949 (2004-12-01), Wang et al.
patent: 2005/0065762 (2005-03-01), Hayashi
patent: 2005/0125751 (2005-06-01), Miller et al.
patent: 2005/0172246 (2005-08-01), Logie et al.
patent: 2005/0185351 (2005-08-01), Miller et al.
patent: 2005/0201031 (2005-09-01), Furuta
patent: 2006/0001100 (2006-01-01), Kamei et al.
patent: 2006/0109596 (2006-05-01), Hayashi
patent: 2007/0165344 (2007-07-01), Esmark et al.
patent: 2008/0043390 (2008-02-01), Yoshitani et al.
patent: 2008/0104554 (2008-05-01), Kobayashi et al.
patent: 2008/0148199 (2008-06-01), Bell et al.
Amerasekara et al., “Failure modes, reliability issues and case studies”, ESD in silicon integrated circuits, 2002.
A. Z. Wang, H.G. Feng, K. Gong, R. Y. Zhan, J. Stine, “On-chip ESD Protection design for integrated circuits: an overview for IC designers”, pp. 733-747, Microelectronic Journal, May 2001.
Hirokazu Hayashi, Toshikazu Kuroda, Katsuhiro Kato, Koichi Fukuda, Shunsuke Baba, and Yasuhiro Fukuda, “ESD Protection Design Using a Mixed-Mode Simulation for Advanced Devices”, EOS/ESD Symposium Digest 2004.
H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, A. Z. Wang, R. Gafiteanu, “A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology”, pp. 995-1006, IEEE Journal of Solid-State Circuits, Jun. 2003.

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