Fishing – trapping – and vermin destroying
Patent
1989-03-06
1992-09-01
Thomas, Tom
Fishing, trapping, and vermin destroying
437 47, 437 48, 437 60, 437192, 437228, H01L 2170
Patent
active
051438615
ABSTRACT:
A method for forming a memory cell for a dynamic random access memory includes the steps of first forming the transistors having gate electrodes (34) and source/drain regions (44) on either side thereof. An isolation trench (48) is formed in one of the source/drain regions with a portion (52) remaining. A masking layer (56) is formed over the surface of the substrate and an opening (62) formed therein to expose the source/drain region (52) and associated tungsten layer (50). A conductive plug (62) is formed in the opening followed by formation of an oxide layer (66). The plug (62) comprises the lower plate of the capacitor and then a conformal layer of conductive material (68) is formed over the surface thereof to comprise the upper plate of the capacitor. A planarized layer of oxide (69) is formed over the substrate and an opening (70) formed therein to expose the other of the source/drain regions (44). A contact plug (76) is formed in the opening (70) followed by formation of the interconnect layer (78).
REFERENCES:
patent: 4495219 (1985-01-01), Kato et al.
patent: 4644386 (1987-02-01), Nishizawa
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4855801 (1989-08-01), Kuesters
patent: 4951175 (1990-08-01), Kurosawa
patent: 4958318 (1990-08-01), Harari
patent: 4961165 (1990-10-01), Ema
International Electron Devices Meeting, pp. 246-249, Dec. 14, 1988.
Trends and Directions in VLSI Memory Technology, vol.3, pp. 1056-1061, Aug. 25-28, 1987.
Hill Kenneth C.
Howison Gregory
Jorgenson Lisa K.
SGS-Thomson Microelectronics Inc.
Thomas Tom
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