Method in the manufacture of integrated circuits

Details Method in the manufacture of integrated circuits Method in the manufacture of integrated circuits

1986-10-30

1988-04-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437202, 437193, 357 71, H01L 2188, H01L 2190, H01L 2350

Patent

active

047404841

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a method in the manufacture of integrated circuits.
When miniaturizing the dimensions of integrated circuits, such as so-called NMOS-circuits and CMOS-circuits, it has been found that gate-conductors and connecting conductors made of polycrystalline silicon in accordance with predominantly prevailing methods constitute a limiting factor with regard to the performance of the circuits. This is because these conductors have an excessively high resistance, which results in RC-type time constants of such magnitudes as to restrict the speed of the circuits.
In order to reduce the resistance in the conductors, the polycrystalline silicon gate-conductors have been provided with a metallic, conductive top layer. This reduces the resistance of the conductors by a factor of 10 to 20.
The metal layers deposited on the conductors must be stable at temperatures of up to about 900.degree. C., since the metal layer is deposited prior to activation of ion implantations. This restricts the choice of the silicide used to one which is stable at high temperatures, such as WSi.sub.2, TaSi.sub.2, MoSi.sub.2, and TiSi.sub.2 or refractory metals, such as tungsten (W).
In the case of circuit elements of micrometer-size, or of smaller size, it has been found that the doped conductive surfaces located adjacent the gate-structure, i.e. the so-called source-and-drain-areas, must also be metallized, in order to improve their surface conductivity.
This is effected by siliciding, i.e. depositing a metal which reacts with silicon present in the doped areas, to form therewith a metallic conductive silicide.
Consequently, in the case of integrated circuit elements of the aforesaid dimensions, it is necessary to metallize both the gate electrodes, conductors and the source-and-drain-areas.
In accordance with one known method, platinum is deposited onto the circuit, when provided with gate structures and conductors and when parts of the circuit which are not to be metallized comprise silicon oxide. The circuit structure is then heated, so that the platinum reacts with the silicon present, to form a silicide. Non-reacted metal is then removed from the silicon-oxide surfaces with the aid of a selective etching process, i.e. a process which does not affect metallized silicon. The advantage afforded by this technique is that precise measurements can be achieved with regard to the extensions of the metallized surfaces, without needing to machine the elements concerned.
In order to avoid the occurrence of short-circuits between the source-and-drain-areas and the gate electrode, there has been developed a technology in which an insulating layer is built-up between the source-and-drain-areas and the gate electrode. In this case, the gate electrode and source-and-drain-areas are metallized subsequent to forming the insulating layer. A suitable metal is deposited over the circuit, whereafter the circuit is heat-treated to cause the metal to react with the polycrystalline silicon of the gate electrode and with the monocrystalline silicon of the source/drain areas. Metal located outside the metallized areas is then etched away, with the aid of a selective etching process, while leaving the insulating layers intact. This method is called the SALICIDE-process.
All of the aforedescribed methods have a common drawback, namely that the same silicide must be used on both the gate and the source/drain areas. It follows from this that mutually different silicides cannot be chosen for the various areas to be treated. It is highly desirable to be able to choose different silicides for the gate electrodes and the source/drain areas.
A further disadvantage with the SALICIDE-process is that despite the presence of the insulating layers it is difficult to eliminate the occurrence of short-circuiting between the gate electrodes and the source/drain areas, due to the necessity of using high-temperature silicides.
The insulating layers comprise, for example, silicon nitride. At the high temperatures applied in the metallizing process, sili

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Ting, "Silicide for Contacts and Interconnects", IEDM Technical Digest, 1984, pp. 110-113.
Alperin et al, "Development of the Self-Aligned Titanium Silicide Process for VLSI Applications", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 61-67.
Jones et al, "Salicide with Buried Silicide Layer", IBM Technical Disclosure Bulletin, vol. 27, No. 2, Jul. 1984, pp. 1044-1045.
Adler et al, "Process for Fabricating Field-Effect Transistors with Polysilicon Gates Containing Metal Silicide", IBM Technical Disclosure Bulletin, vol. 26, No. 5, Oct. 1983, pp. 2309-2310.
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