Method in the fabrication of a silicon bipolar transistor

Details Method in the fabrication of a silicon bipolar transistor Method in the fabrication of a silicon bipolar transistor

2000-11-24

2002-08-27

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S318000, C438S345000

Reexamination Certificate

active

06440810

ABSTRACT:

TECHNICAL FIELD
The invention relates to silicon bipolar transistors, especially low-voltage high-frequency transistors for use in mobile telecommunications, and particularly it relates to a method in the fabrication of such transistors.
TECHNICAL BACKGROUND
The Problem Area
Bipolar integrated circuits play a major role for modern telecommunication systems. The circuits are used mostly for analog functions, e.g. for switching currents and voltages, and for high-frequency radio functions (mixers, amplifiers, detector etc.).
To achieve good high-frequency properties of the transistor, the base must be made very narrow. Several problems from the physics and practical point of view arise. The doping of the base must be carefully tuned to give a reasonable beta, not too high doping in the emitter-base junctions (low BV
ebo
will follow otherwise), enough doping to withstand voltage applied over the base without going into “punch-through” breakdown, the Early voltage should be high, base resistance should be low, etc.
An important feature of high-frequency high-performance bipolar transistors is the emitter-base region. A polysilicon emitter improves the current gain and reduces the emitter charge storage time, and a narrow base reduces the base transit time and thus improves the high-frequency properties of the device. The base is usually formed by ion implantation of boron. The preferred shape of a thin base doping is a box, but with ion implantation, a smooth, almost half-triangular shape is usually obtained. A solution to this problem is to epitaxially deposit an in-situ doped base layer, thus obtaining a box profile structure. An extension of this is the epitaxially grown SiGe-transistor, where 10-30% Ge is added into the base to create heterojunction devices, that may improve the high-frequency properties and the current gain of the device.
To obtain transistors well suited e.g. for telecommunication applications, not only a low transit time (high f
T
) is needed, but also a high maximum oscillation frequency (f
max
) is required. To do this, the transistor must also have low collector-base capacitance and low base resistance. The base resistance consists of intrinsic and extrinsic base resistance and contact resistance.
Bipolar high-frequency transistors usually utilizes a self-registered base-emitter structure described in T. H. Ning et al., “Self-aligned NPN bipolar transistors”, IEDM Tech. Dig., pp. 823-824, 1980, in which the transistor cell can be made smaller than with other techniques. Furthermore, reduced base-collector capacitance and reduced base resistance are obtained when the extrinsic base is contact to the intrinsic base close to the emitter. Several variations of the concept are known.
In U.S. Pat. No. 5,266,504 by Blouse et al., a method is described for manufacturing a self-aligned bipolar transistor, where the base is epitaxially grown, a polysilicon layer for the extrinsic base deposited but removed over the intrinsic base (no details are given how etch selectivity was obtained), and the emitter is formed by deposition of an amorphous silicon layer followed by patterning and etching. The amorphous silicon is re-crystallized by Solid Phase Epitaxy (SPE), and thus a sharp and well-controlled emitter-base junction is achieved. The re-crystallization is made by a prolonged heating (4 to 8 hours).
In U.S. Pat. No. 5,593,905 by Johnson & Taylor, a method is described for manufacturing a self-aligned bipolar transistor, where a link layer is formed between the intrinsic and extrinsic base, consisting of a double-layer of doped oxide and nitride, which is then pattern to cover the intrinsic base area only. The polysilicon for the extrinsic base is then deposited and the emitter window opened in the polysilicon, using the double-layer as an etch stop. The layer is then removed by dry-etching, stopping at the substrate (the base), using an etch that is highly selective against silicon. This etch reduces the damages to the active area as would have been the case as if polysilicon would have been etched directly on top of silicon. However, the method requires an additional mask layer, compared to conventional processing.
Patent WO 9719465, by Norstrom, utilizes different properties of amorphous silicon and the silicon substrate to add doping to the extrinsic base in a controlled way, and to open the emitter window with better properties than obtained by conventional processing.
Problems of Known Solutions
A common problem when fabricating self-aligned double-polysilicon bipolar transistors using thin bases is how to form the extrinsic base region (thick, heavily-doped material) and the intrinsic base region (thin, precise doping profile) and how to integrate this with the formation of the emitter.
The main problem occurs when the emitter window is to be opened. This usually involves etching of a polycrystalline layer on the silicon substrate. The problem is how to stop the etching procedure so that the polycrystalline layer is fully removed without etching down into the substrate. The problem is further accentuated if a thin base region formed via e.g. epitaxy prior to polysilicon deposition and etching of the emitter windows. The polycrystalline layer is preferentially etched along different crystal orientations and grain boundaries, which gives etching residues (pillars), non-uniformities (facets) and uneven edges in the etched areas. Especially when etching the emitter window, the etching properties is a major concern, since etching into the substrate (the intrinsic base), the base may be damaged or the link region between intrinsic and extrinsic base may be made too thin, causing high base resistance or even unlinking the intrinsic base from the extrinsic base. Emitter pipes may also occur because of etching residues (pillars), which can cause emitter leakage currents.
Ion implantation into polycristalline materials is not an optimal choice if good doping profile control is required. Because of channeling of the implanted species in polycristalline material, it may be hard to precisely control the doping profile. Implanting into similar amorphous layers solves the problem.
A method where the silicon for extrinsic base contacts is removed in the emitter window without affecting the underlying base layer is therefore of need.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of fabrication a semiconductor structure that avoids the problems mentioned above by utilizing a thin oxide as etch stop when opening the emitter window in a self-aligned silicon bipolar transistor.
This object among others is, according to one aspect of the invention, attained by a method for forming base regions and for opening an emitter window, comprising the steps of:
providing a silicon substrate with suitable device isolation;
forming a first base region in or on top of said substrate;
forming a thin layer of oxide on said first base region;
forming a layer of silicon on top of said thin oxide layer, said silicon layer is to be a second base region;
ion implanting said silicon layer;
forming a layer of a dielectric on top of said silicon layer, said dielectric is to isolate base and emitter regions of said transistor;
patterning the hereby obtained structure in order to define the emitter window;
etching the structure inside said defined emitter window area and through the dielectric and silicon layers, wherein the thin oxide layer is used as etch stop, thus forming the emitter window; and
subsequently heat treating the structure and thus break up the oxide such that the first and second base regions will contact each other.
Conventional processing steps may finish the transistor.


REFERENCES:
patent: 4641416 (1987-02-01), Iranmanesh et al.
patent: 4704785 (1987-11-01), Curran
patent: 5028557 (1991-07-01), Tsai et al.
patent: 5266504 (1993-11-01), Blouse et al.
patent: 5541124 (1996-07-01), Miwa et al.
patent: 5592017 (1997-01-01), Johnson
patent: 5593905 (1997-01-01), Johanson et al.
patent: 5600177 (1997-02-01), Yamazaki
patent: 5643805 (1997-07-01),

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