Method in an integrated circuit (IC) manufacturing process...

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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Details

C702S082000, C700S116000, C700S224000, C700S226000, C438S014000

Reexamination Certificate

active

06208947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit (IC) manufacturing and, more specifically, to methods in IC manufacturing processes for identifying and redirecting IC's mis-processed during their manufacture.
2. State of the Art
As shown in
FIG. 1
, a typical process
10
for manufacturing very small electronic circuits referred to as “Integrated Circuits” (IC's) begins with the IC's being formed or “fabricated” on the surface of a wafer
12
of semiconductor material, such as silicon. Once fabricated, IC's are electronically probed to determine whether they are functional (i.e., “good”) or nonfunctional (i.e., “bad”), and a computer then stores an electronic wafer map
14
of the wafer
12
identifying the locations of the good and bad IC's on the wafer
12
.
After being probed, IC's are sawed from their wafer
12
into discrete IC dice or “chips” using high-speed precision dicing equipment. IC dice identified as good by their wafer map
14
are then each “picked” by automated equipment from their sawed wafer
12
and “placed” on an epoxy coated bonding site of a lead frame, while IC dice identified as bad are discarded into a scrap bin
16
. The epoxy attaching the good IC dice to their lead frames is then allowed to cure, and the attached dice are wire bonded to their lead frames using high speed bonding equipment. At this point in the process
10
, the lead frames of IC dice are still connected to other lead frames.
Once wire bonded, IC dice and their lead frames are formed into IC packages using a hot thermosetting plastic encapsulant injected into a mold. Leads of the lead frames project from the IC packages after encapsulation, and these leads are dipped in a cleansing chemical bath in a process referred to as “de-flash.” After de-flash, IC packages are cured to set their plastic encapsulant, and their projecting leads are then electroplated with a lead/tin finish.
After lead finishing, connections between the lead frames of different IC packages are cut to “singulate” the IC packages into discrete IC devices. Discrete devices are then tested in a simple electronic test that checks for “opens” (i.e., no connection) within the devices where connections should exist and “shorts” (i.e., a connection) where connections should not exist. Devices that fail the opens/shorts test are discarded into the scrap bin
16
, and devices that pass proceed to extensive back-end test procedures where they are tested for functionality and operability before being shipped to customers.
On occasion, bad IC dice are accidentally picked from a sawed wafer
12
for subsequent assembly and back-end testing as described above. This can happen, for example, because a human, software, or electronic error causes the automated pick and place equipment described above to access the wrong wafer map
14
for a wafer
12
. It can also happen because of a misalignment, referred to as a “registration” error, between the automated pick and place equipment and a wafer
12
. In either case, such accidents typically are not detected until the bad IC dice undergo at least some back-end testing and, as a result, waste back-end testing resources. Therefore, there is a need in the art for a method of identifying and discarding accidentally assembled IC dice before the dice undergo back-end testing procedures.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some methods have been devised to electronically identify IC dice. Such methods take place “off” the manufacturing line, and involve the use of electrically retrievable identification (ID) codes, such as so-called “fuse ID's,” programmed into individual IC dice to identify the dice. The programming of a fuse ID typically involves selectively blowing an arrangement of fuses or anti-fuses in an IC die so that when the fuses or anti-fuses are accessed, they output a selected ID code. Unfortunately, none of these methods addresses the problem of identifying and discarding accidentally assembled IC dice “on” a manufacturing line.
SUMMARY OF THE INVENTION
The present invention provides a method that can identify and discard accidentally assembled integrated circuit (IC) dice “on” an IC manufacturing line before the dice undergo back-end testing procedures.
In one embodiment, the method identifies and redirects IC's that have been misprocessed, such as bad IC's identified at probe that have accidentally been assembled and packaged. The method includes storing data, such as an electronic wafer map, at probe, for example, in association with a unique identification (ID) code, such as a fuse ID, of each of the IC's. The stored data indicates a process flow within the IC manufacturing process that each of the IC's should undergo. For example, the stored data may indicate that an IC is bad and should be discarded, or that an IC is good and should be assembled and packaged.
As described above, on occasion, one or more IC's do not undergo the process flow they should undergo. For example, some bad IC's may proceed through assembly and packaging rather than being discarded. To check for IC's that have not undergone the process flow they should undergo, the present method also includes reading the ID code of each of the IC's at, for example, the opens/shorts test at the end of assembly. The data (e.g., the wafer map) stored in association with the ID code of each of the IC's is then accessed and evaluated to identify any IC's that have undergone a process flow within the IC manufacturing process that is different from the process flow their data indicates they should have undergone, such as bad IC's that have proceeded through assembly and packaging. Any IC's identified as having been mis-processed are then redirected within the IC manufacturing process. Thus, for example, bad IC's that have been assembled and packaged may be discarded so they do not proceed to back-end testing.
In another embodiment of the present invention, a method of manufacturing IC devices, such as Dynamic Random Access Memory Devices (DRAM's), from semiconductor wafers includes providing the semiconductor wafers and fabricating IC's on the wafers. A substantially unique ID code, such as a fuse ID, is then stored in each of the IC's, and data is stored in association with the ID code of each of the IC's that indicates a manufacturing process flow that each of the IC's should undergo. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices, such as wire bond/lead frame devices, Chip On Board (COB) devices, or flip-chip devices. The ID code associated with each of the IC devices is then read, and the data stored in association with the ID code associated with each of the IC devices is accessed and evaluated to identify any IC devices that have undergone a manufacturing process flow that is different from the manufacturing process flow their data indicates they should have undergone. These identified IC devices are then redirected (e.g., discarded), and the remaining IC devices continue on to back-end testing.
A further embodiment of the present invention comprises a method of manufacturing Multi-Chip Modules (MCM's) similar to the method of manufacturing IC devices described above.
A still further embodiment of the present invention comprises another method of manufacturing IC devices from semiconductor wafers. The method includes providing the semiconductor wafers and fabricating IC's on the wafers. Each IC is electronically probed to identify good and bad IC's on the wafers and then programmed with a unique fuse ID. An electronic wafer map is stored for each wafer indicating the locations of good and bad IC's on the wafer and associating each IC on the wafer with its fuse ID. Each IC is then sawed from its wafer to form a discrete IC die that is automatically picked and placed on an epoxy coated bonding site of a lead frame

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