Method for zero byte time slot interchange

Details Method for zero byte time slot interchange Method for zero byte time slot interchange

1986-12-22

1988-07-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701101, H04J 300, H04J 312

Patent

active

047574992

ABSTRACT:
This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. Intermediate storage octets are utilized to contain addresses of an all zero octet. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.

REFERENCES:
patent: 4254461 (1981-03-01), Chemla et al.
patent: 4394759 (1983-07-01), Delle Donne
patent: 4685100 (1987-08-01), Coppers et al.

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