Method for wafer scale testing of redundant integrated circuit d

Details Method for wafer scale testing of redundant integrated circuit d Method for wafer scale testing of redundant integrated circuit d

1990-06-01

1991-10-01

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 226, G01R 3128, G06F 1126

Patent

active

050537008

ABSTRACT:
A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuit dies should shorting occur during dicing. The integrated circuit dies and wafer scale test system may optionally be partitioned into several separate groups to prevent faults in the interchip multiplexor system from rendering the entire wafer useless.

REFERENCES:
patent: 3710251 (1973-01-01), Hagge et al.

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