Etching a substrate: processes – Planarizing a nonplanar surface
Reexamination Certificate
2000-02-22
2003-02-04
Olsen, Allan (Department: 1746)
Etching a substrate: processes
Planarizing a nonplanar surface
C216S053000, C216S089000, C216S099000
Reexamination Certificate
active
06514423
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor wafer processing, and in particular to a method for preparing peripheral edges of wafers that employs mechanical burnishing.
Semiconductor wafers are generally prepared from a single crystal ingot, such as a silicon ingot, which is sliced into individual wafers. Each wafer is subjected to a number of processing operations to facilitate the installation of integrated circuit devices and to improve their yield, performance, and reliability. Typically, these operations reduce the thickness of the wafer, remove damage caused by the slicing operation, and reduce surface roughness.
Each wafer must undergo processing not only on at least one of its flat, facial surfaces but also along its peripheral edge or rim. Typically, each wafer is shaped along its edge with a grinding tool to remove square corners and to form a desired edge cross-section profile. That grinding causes substantial micro-crack and chip damage. During subsequent handling and processing, edges receive impact forces and relatively high local stresses that produce additional fractures, pits, and roughness. If left in place, these imperfections permit nucleation of damage to the crystal lattice. They increase the likelihood that slips and dislocations will grow and potentially ruin the wafer. Further, edge roughness tends to facilitate adherence of impurities, such as dust particles and inorganic anions, that can diffuse from the edge to facial surfaces where they detrimentally contaminate the wafer. Accordingly, the edge of each wafer must be smoothed to remove imperfections or reduce their size.
One method that is widely used in wafer processing to smooth surfaces is chemical-mechanical polishing. It generally involves rubbing a wafer with a soft polishing pad, such as a polyurethane impregnated polyester felt, while dispensing a polishing solution, or slurry. The slurry contains an abrasive and chemicals, such as a colloidal silica and an alkaline etchant, so that both mechanical action and chemical reaction contribute to the removal of material. The results are wafer surfaces that are flat, highly reflective, and damage-free. However, there are drawbacks to chemical-mechanical polishing. Polishing machines are relatively expensive. The slurry also has a high cost, and it is typically a toxic, alkaline fluid. It requires careful handling by operators and introduces problems relating to safe environmental waste treatment and disposal.
Although chemical-mechanical polishing is crucial for wafer facial surfaces, it is not absolutely necessary along edges because the required standard for smoothness is not as stringent. Nevertheless, many edge smoothing methods are based on chemical-mechanical edge polishing, and they bring the associated drawbacks of cost and complexity. Edge polishing takes substantial time and is a hindrance to achieving high throughput in the processing of wafers.
As an alternative to polishing, wafer edges have been burnished to smooth edge surfaces. Burnishing comprises rubbing an abrasive appliance along the edge to remove surface layers of semiconductor material. A stream of liquid water is typically provided to cool the wafer and eliminate abraded material, but there is no polishing solution or chemical slurry. Thus, unlike polishing, burnishing entails no chemical reaction. Material is removed solely by mechanical action. One type of edge burnishing machine is disclosed in U.S. Pat. No. 5,509,850. That machine includes a thin, flexible tape coated with abrasive particles that is rubbed against an edge of a wafer at varying elevational angles while being oscillated laterally. The tape rapidly removes material from the edge.
Burnishing machines offer the potential for significantly reduced-cost edge processing. Burnishing machines have a lower initial cost than edge polishing machines, and they avoid the expense of slurry and its handling and disposal complications. Burnishing can be performed much more rapidly than polishing, improving throughput between 50% and 100%.
However, burnishing an edge is only one step within a method for wafer processing and, in isolation, is insufficient to adequately smooth the edge. Although burnishing removes surface layers and eliminates large imperfections to afford some smoothing, it introduces new, smaller imperfections and damage. Specifically, any mechanically abrasive removal, as in burnishing, necessarily produces some damage because the abrasive is harder than the semiconductor material and high pressure is applied to obtain penetration and material removal. New microcracks and roughness due to burnishing are much smaller than previous damage, but nevertheless unacceptably large. A complete method for processing a wafer that includes edge burnishing, as well as other steps to produce an acceptably smooth wafer on the edge and the facial surfaces, has not been defined.
SUMMARY OF THE INVENTION
Among the several objects and features of the present invention may be noted the provision of a method for processing a peripheral edge of a semiconductor wafer that improves throughput in the preparation of wafers; the provision of a such a method that simplifies; the provision of such a method that smooths the edge without using a polishing slurry on the edge; and the provision of a method that reduces wafer processing costs.
In general, a method according to the present invention for processing a semiconductor wafer reduces surface roughness. The wafer has two flat, opposite faces with a peripheral edge extending around a circumference of the wafer between the faces. The method comprises, in the following order, the steps of burnishing the edge, and etching the edge. The step of burnishing is defined by a relative rubbing motion between the edge and an abrasive appliance to remove damage from the edge, the rubbing motion occurring free from any polishing solution or chemical slurry. The step of etching includes exposing the wafer to a liquid chemical etchant for a period of time to remove additional damage from the edge.
In another aspect, a method according to the present invention for processing a semiconductor wafer reduces surface roughness. The wafer has two flat, opposite faces with a peripheral edge extending around a circumference of the wafer between the faces. The method is an improvement to a method of a type having, in the following order, the steps of lapping at least one face of the wafer, etching the wafer by exposing the wafer to a liquid chemical etchant, conducting chemical-mechanical polishing of the peripheral edge of the wafer with a first polishing pad and a polishing slurry, and conducting chemical-mechanical polishing of the face of the wafer with a second polishing pad and a polishing slurry. The improvement comprises adding a step, after the step of lapping and prior to the step of etching, of burnishing the peripheral edge, and deleting the step of conducting chemical-mechanical polishing of the peripheral edge.
In yet another aspect, a method according to the present invention for processing a semiconductor wafer reduces surface roughness. The wafer has two flat, opposite faces and a peripheral edge extending around a circumference of the wafer between the faces. The method comprises, in the following order, the steps of lapping at least one face of the wafer to remove semiconductor matter through a relative rubbing motion between the face and an abrasive lapping plate in the presence of an abrasive liquid slurry. The peripheral edge of the wafer is burnished to remove semiconductor matter and embedded imperfections through a relative rubbing motion between the edge and an abrasive appliance, the rubbing motion occurring free from any polishing solution or chemical slurry. The wafer is etched to remove additional semiconductor matter and embedded imperfections by exposing the wafer to a liquid chemical etchant for a period of time.
Other objects and features of the present invention will be in part apparent and in part pointed out hereinafter.
REFERENCES:
Ng Kan-Yin
Teasley Brent
MEMC Electronic Materials , Inc.
Olsen Allan
Senniger Powers Leavitt & Roedel
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