Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-09-21
2002-09-03
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S118000, C438S119000, C438S455000, C438S459000
Reexamination Certificate
active
06444493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for vertically integrating two active circuit planes. In addition, the present invention relates to vertically integrated circuits produced by means of such methods.
2. Description of Prior Art
Integrated circuits arranged in a substrate are located essentially in the vicinity of a main surface of the substrate. In integrated circuits the active life of the transistors takes place only in the uppermost plane of the substrate, e.g. of the silicon crystal, in a thickness range of less than 2 &mgr;m. The residual, a few hundred microns thick silicon of the substrate is not required for the circuit function. Hence, increasing efforts have been made for some time to utilize the third dimension, i.e. the thickness dimension more effectively.
The production of an integrated circuit e.g. in CMOS technology normally comprises far more than 100 individual process steps; each of these process steps must be mastered separately with a yield of approx. 100% so as to obtain a reasonable yield. Attempts to build up further circuit planes by further processing on existing planes so as to directly integrate an additional circuit plane in this way would mean that twice the number of process steps has to be carried out, whereby the demands on the yield would increase exponentially. Hence, such a utilization of the thickness dimension cannot be realized in a sensible way.
The joining of two wafers which have been: processed independently of one another will, however, only entail a small number of additional steps for the individual wafer. More recent solutions are therefore based on the stacking of fully processed chips, the contacts protruding on one side and being wired together. Such techniques are disclosed e.g. in M. F. Suer, et al: High Density 3D Packaging”, Proc. VLSI Packaging Workshop (1991), and C. L. Bertin, et al: “Evaluation of a Three-Dimensional Memory Cube System”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 16(8), p. 1006, (1993). These methods are, however, only suitable for components having a small number of terminals, e.g. for storage components, but not for logic units having a large number of terminals.
Other concepts are based on three-dimensional multichip module techniques (3D-MCM techniques). In the case of these techniques several multichip modules are stacked one on top of the other. This is done in such a way that one or a plurality of chips are mounted on a support so as to define a multichip module in common, whereupon a plurality of supports is joined and wired together. Such techniques are described e.g. in H. Nakanishi, et al: “Development of High Density Memory IC Package by Stacking IC Chips”, Proc. IEEE Electronic Components and Technology Conference, p. 634 (1995); C. G. Massit, G. C. Nicolas: “High Performance 3D MCM Using Microtechnologies”, Proc. IEEE Electronic Components and Technology Conference, p. 641 (1995); J. Barret, et al: “Performance and Reliability of a Three-Dimensional Plastic Moulded Vertical Multichip Module (MCM-V)”, Proc. IEEE Electronic Components and Technology Conference, p. 656 (1995); and they are also described in U.S. Pat. No. 5,202,754.
DE 4433846 A, DE 4433845 A, DE 4433833 A and U.S. Pat. No. 5,563,084 additionally describe vertical integration methods which are based on a so-called interchip-via concept (ICV concept). According to this concept, wafers are first processed by means of standard processes. Then, two wafers are joined, the upper wafer being thinned to a thickness of approx. 10 &mgr;m for the purpose of stacking and being then glued onto the lower wafer. Subsequently, the electric connections between the upper plane and the lower plane are established by means of a trench production method which is normally used in the field of semiconductor technology, but which has been modified. When the ICV concept is used, the active side of the respective wafer is arranged on the top so that the stacking of a plurality of planes is, in principle, possible, but the contacts from one plane to the next must be passed through the wafer. For this through connecting processes are necessary which require temperatures above 400° C. The ICV concept is additionally disadvantageous insofar as auxiliary supports are required for thinning the upper wafer and that complicated rebonding processes have to be carried out consequently.
DE 44 27 515 C1 describes a method for producing a three-dimensional circuit arrangement comprising the steps of glueng a substrate disc, which comprises components in a first main surface thereof, onto a supporting plate, thinning it and dicing it by an etching process, after the application of a photoresist mask, making use of the photoresist mask as an etching mask, so that splintering of the thinned substrate discs is avoided and so that a better utilization of the material is achieved.
DE 42 38 137 A1 describes a method for producing devices with components, which are produced from,various materials.
DE 195 16 487 C1 discloses a method for vertically integrating microelectronic systems in the case of which two substrates are connected front to front. The term front here describes the side of the substrate on which circuit layers and associated metallizations are formed. A first substrate is prepared by forming a viahole therein from the front of the substrate; this viahole fully penetrates at least the circuit layers and it extends through a metallization on the front of the first substrate. Subsequently, the front of the first substrate is joined to the front of a second substrate, the metallization on the front of the first substrate being in alignment with a metallization on the front of the second substrate. After the joining, the aligned metallizations on the first and on the second substrate are not interconnected in an electrically conductive manner. This electrically conductive connection is achieved in that the first substrate is thinned to such an extent that the viahole is open at the back, whereupon insulating layers on top of the metallization of the second substrate are removed through the viahole so that the metallizations on the first and second substrates are connected in an electrically conductive manner by filling the viahole with a conductive material.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a method for vertically integrating active circuit planes which permits a substantial simplification of process control.
This object is achieved by a method for vertically integrating active circuit planes in the case of which a first substrate comprising at least one integrated circuit in a first main surface thereof and further comprising connecting areas for the integrated circuit as well as outer connecting areas on the first main surface is provided in a first step. In addition, a second substrate comprising at least one integrated circuit in a first main surface thereof and further comprising connecting areas for the integrated circuit as well as open or openable areas on the first main surface thereof is provided. The first main surfaces of the first and second substrates are joined in such a way that the connecting areas of the first substrate are connected to those of the second substrate in an electrically conductive manner in such a way that the outer connecting areas of the first substrate are in alignment with the open or openable areas of the second substrate. Subsequently, the second substrate is thinned and the outer connecting areas are exposed through the open or openable areas.
The present invention is preferably so conceived that the first and the second substrate are a first and a second wafer, each comprising a plurality of integrated circuits arranged in the first main surface thereof and connecting areas arranged on the first main surface and associated with the respective integrated circuits. The first main surface of the first substrate or first wafer may have provided thereon outer connecting areas which, after
Feil Michael
Landesberger Christof
Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung
Lee Eddie
Patton & Boggs LLP
Richards N. Drew
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