Method for verifying protocol conformance of an electrical inter

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364578, 710 8, 710113, G06F 1900, G06G 748

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active

059663065

ABSTRACT:
A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a "clean bus" theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.

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Gerald J. Holzmann, "Design and Validation of Computer Protocols," Synopsis, Prentice Hall, 1991, Chapter listing only, full book available to "Researchers and professionals".

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