Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
2011-07-12
2011-07-12
Silver, David (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C703S027000, C716S106000
Reexamination Certificate
active
07979262
ABSTRACT:
Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets. Verifications can be performed for both digital and mixed signal digital/analog designs without running simulations.
REFERENCES:
patent: 5202841 (1993-04-01), Tani
patent: 5249133 (1993-09-01), Batra
patent: 5351197 (1994-09-01), Upton et al.
patent: 5473546 (1995-12-01), Filseth
patent: 6405351 (2002-06-01), Steiss et al.
patent: 6421808 (2002-07-01), McGeer et al.
patent: 2002/0124234 (2002-09-01), Linz
patent: 2004/0193388 (2004-09-01), Outhred et al.
patent: 2005/0144578 (2005-06-01), Decloedt
patent: 2005/0198600 (2005-09-01), Hasegawa
patent: 2006/0074626 (2006-04-01), Biswas et al.
patent: 2007/0061764 (2007-03-01), Adams et al.
Accellera, Verilog-AMS, Language Reference Manual, Analog & Mixed-Signal Extensions to Verilog HDL, Version 2.2, Nov. 2004.
Chetput Chandrashekar L.
Iyengar Srinivasan
Kolpekwar Abhijeet
Cadence Design Systems Inc.
Silver David
Vista IP Law Group LLP
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