Method for verifying circuit layout design

Details Method for verifying circuit layout design Method for verifying circuit layout design

1992-01-24

1995-09-12

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

054503310

ABSTRACT:
The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e.g., minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.

REFERENCES:
patent: 4554625 (1985-11-01), Otten
patent: 4791586 (1988-12-01), Maeda et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4829446 (1989-05-01), Draney
patent: 4872103 (1989-10-01), Kingsley
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5062054 (1991-10-01), Kawakami et al.
patent: 5065355 (1991-11-01), Hayase
patent: 5113451 (1992-05-01), Chapman et al.
patent: 5151868 (1992-09-01), Nishiyama et al.
patent: 5202841 (1993-04-01), Tani
"Programs for Verifying Circuit Connectivity of MOS/LSI Mask Artwork" by Takashima et al., IEEE 19th Design Automation Conference 1982, pp. 544-550.

Affiliated with

Also associated with

Rating

Method for verifying circuit layout design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for verifying circuit layout design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for verifying circuit layout design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-410446