Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-09-18
2011-11-08
Lin, Sun (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S104000, C716S106000, C716S108000
Reexamination Certificate
active
08056037
ABSTRACT:
The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.
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Koehl Juergen
Pietschmann Walter
Saalmueller Juergen
Schumacher Norbert
Urban Volker
International Business Machines - Corporation
Lin Sun
Seal Cynthia G.
Yee & Associates P.C.
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