Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-03-26
2001-04-03
Nguyen, Chau (Department: 2739)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S395430
Reexamination Certificate
active
06212181
ABSTRACT:
1. Field of the Invention
The present invention relates generally to transferring information over a network. More particularly, the present invention relates to an improved memory arbitration system used in transferring information between devices in a network.
2. Background of the Invention
Modern network devices transfer information using a protocol such as the asynchronous transfer mode (ATM) protocol in which data is transferred in “cells,” or fixed-length packets. In a shared memory switch, each data cell is stored in a memory device (typically Dynamic Random Access Memory or DRAM) before being transmitted towards its destination. The memory device for storing data cells is typically referred to as cell memory. As each cell arrives, an arrival engine determines where to store the cell in cell memory. A departure engine chooses a cell to retrieve from cell memory for transmission. A cell memory controller executes the instructions from the arrival and departure engines, to transfer the cell to or from the cell memory, typically on a timeslot basis.
Data arriving at the arrival engine may include external data and internal data. External data arriving from an external source (such as a physical line) typically cannot be throttled because the source of the data does not respond to feedback signals from the arrival engine. Thus, flow control is unavailable. When external data arrives, the data is written to the cell memory.
The arrival engine also handles internal data. Internal data, such as operation and maintenance cells, is typically internally generated traffic or data which arrives from a control plane. Internal data is typically assigned a low priority because flow control is available to slow the flow of internal data without loss of data. However, the system receiving the data generally guarantees a specified minimum bandwidth to the internal data. Failure to provide such a minimum bandwidth may result in a “starvation” situation. Thus, when the minimum bandwidth is not provided, the internal data is assigned a higher priority.
A circuit element such as a cell memory receiving arrival data also outputs departure data. Thus, current systems maintain a predetermined bandwidth for departure data. Current systems are therefore designed to allocate bandwidth to accommodate (1) a maximum external data flow, (2) a minimum bandwidth of internal data, and (3) a minimum transmission of departure data. In order to accommodate such systems, a typical design may divide each memory access opportunity into timeslots, and allocate a fixed number of timeslots to input data and a fixed number of timeslots to departure data.
Such preset systems are typically designed to have excess capacity or to drop data when excessive incoming data arrives.
SUMMARY OF THE INVENTION
A method of assigning timeslots in an asynchronous transfer mode (ATM) switch is described. In the system, a departure timeslot is used to receive arrival cells when no cell departures are scheduled.
In an alternate embodiment, the system prioritizes arrival data and utilizes a departure timeslot for arrival data when high priority arrival data is pending.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Bergen Christopher B.
Divivier Robert J.
Goldman Gary S.
Blakely , Sokoloff, Taylor & Zafman LLP
Cisco Technology Inc.
Lee Chiho Andrew
Nguyen Chau
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