Method for use in simulation of an SOI device

Details Method for use in simulation of an SOI device Method for use in simulation of an SOI device

1997-09-26

2000-02-08

Asta, Frank J.

39550025, 39550041, G06G 748

Patent

active

060235772

ABSTRACT:
A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, NDR rules generation), the offset from the body voltage as a part of the best case/worst case determination is included.

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Krishman et al., "BiMOS modeling for reliable SOI circuit design," SOI Conference 1996 Proceedings, IEEE International, Sep. 1996.

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