Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-09-05
2002-03-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S640000, C438S643000, C438S645000, C438S649000, C438S650000, C438S758000, C438S759000, C438S760000, C438S761000, C438S763000, C438S787000, C438S788000, C438S791000
Reexamination Certificate
active
06358816
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the field of fabrication of semiconductor devices and more particularly to the field of the fabrication of an area of circuitry on a substrate in which the area requires a uniform planar surface for optimal efficiency.
RELATED ART
In the process of manufacturing microelectronic devices it is a common practice to electrically isolate areas in a substrate by etching of trenches around a device or array that are subsequently filled with a dielectric material. Deposition of the dielectric material typically results in an uneven surface, particularly in that the surface contains dips over the area of the trenches. This uneven surface is typically planarized by a chemical mechanical polish (CMP) prior to further processing. Because of the mechanical properties of the pads used in the polishing process, there is a problem with “dishing,” or the surface being non-uniform and more heavily polished near the edges of the device than in or near the center. Because of variations in electrical properties in a device that is not evenly polished, or that does not have a planar surface, such a device may not function properly or it may fail more quickly.
A typical memory device is made of an array of longitudinal active regions wherein the active regions are separated by substantially parallel longitudinal trenches disposed between the active areas. One solution to the problem of uneven polish on the edges of such an array has been to include dummy active regions along the edges of an array in which the dummy regions are chemically (compositionally) and spatially (geometrically) identical to the intended active regions. In this way, the nonplanar edges occur over the dummy active regions and do not affect the actual active array. A memory array such as a nonvolatile memory array that requires higher voltage and is more sensitive to the aberrations caused by a nonplanar surface may require as many as ten dummies along each edge of the array, resulting in a significant loss of usable active area on the substrate.
Another solution to the problem has been the use of dummy tiles, which are tileshaped active regions which are arranged around the array in order to reduce the distortion at the edges of the array. The use of dummy tiles has provided better results than the use of dummy active areas, however dummy tiles must be spaced farther away from the outermost active areas than the spacing of dummy active areas. The dummy tiles are, in fact, often used in conjunction with dummy active areas. Therefore, this method does not solve the problem of the loss of unusable substrate “real estate.” Thus, there is still a need for a method of reducing the distortion at the edges of an array to achieve a planar surface on a wafer or on the dice within a wafer without the loss of space on the substrate due to dummy active areas or tiles.
REFERENCES:
patent: 5920792 (1999-07-01), Lin
patent: 5946592 (1999-08-01), Lin
patent: 5969409 (1999-10-01), Lin
patent: 6060385 (2000-05-01), Givens
Ingersoll Paul A.
Singh Rana P.
Berry Renee R.
Clingan, Jr. James L.
Motorola Inc.
Nelms David
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