Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-19
2003-11-04
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S514000, C438S558000
Reexamination Certificate
active
06642152
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor processing and, more particularly, to a system and method for reducing the linewidth of ultra thin resist features by implanting the ultra thin resist.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist and an exposing source (such as optical light, x-rays, etc.) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The ability to reduce the size of computer chips is driven by lithography technology which, in turn, relies upon decreasing the wavelength of the radiation used in the technology. Currently, 248 nm radiation is widely used in manufacturing while 193 nm radiation is being explored in research and development. Future lithography technologies may progress to 157 nm radiation or even lower wavelengths such as those used in extreme ultra-violet (EUV) lithography (11-13 nm).
As the wavelength of the radiation decreases, organic-based photoresist materials become increasingly opaque to the radiation. This effect necessitates the use of ultra thin resist (UTR) coatings to maintain the desired characteristics of the masked photoresist structures, including maintaining maximum exposure and focus latitude of the masked photoresist structures as well as near vertical sidewalls for the resist profiles. Ultra thin resist coatings, as described here, are generally considered to be resist films of less than 2500 Å in thickness. This compares to conventional lithographic processes which use resist film thicknesses of more than 5000 Å for 248 nm lithography and about 4000 Å for 193 nm lithography.
A conventional lithographic trim process utilizing a resist film having a thickness less than 2500 Å is outlined in FIG.
1
.
FIGS. 2-6
illustrate a structure
20
undergoing the process
10
. In
FIG. 2
, the structure
20
comprising a semiconductor substrate
22
, a device film
24
and a hard mask
28
is shown.
FIG. 3
corresponds to a step
12
(
FIG. 1
) in which a resist layer
32
is deposited over the hard mask
28
. The resist layer
32
has a thickness of greater than 2500 Å.
FIG. 4
illustrates a step
14
(
FIG. 1
) in which the resist layer
32
as shown in
FIG. 3
is patterned using a photomask
40
and incident radiation
36
. The resist layer
32
shown in
FIG. 4
has been substantially etched and developed. In
FIG. 5
, the resist layer
32
has been isotropically etched as prescribed by step
16
(FIG.
1
). As indicated by the dashed line, the linewidth of the resist layer
32
has been decreased as a result of the isotropic etch process. Once the hard mask
28
and the device film
24
have been etched and developed, the structure
20
in
FIG. 6
is obtained. The decreased size of the etched resist layer
32
following the isotropic etch (trim) leads to smaller, but highly flawed or imperfect structures.
Several problems still exist with conventional trim processes. For example, although device films can be scaled down and the selectivity of the etch process can be improved, the increasing use of trim processes can fully consume the etch process margin for the underlying film because some of the resist is consumed during the trim step (leaving less for etching the film). In particular, ultra thin resist coatings can pose problems during etch processes because the device films needing to be etched often do not scale as rapidly as the thickness of the resist coating. In addition, ultra thin resist films do not planarize underlying device topology. The implication of ultra thin resist over topography is that the resist is thinnest over “high” areas and thickest over “low” areas. Naturally, the etch process will be limited by the areas where the resist is thinnest.
Thus, it is a recognized problem that ultra thin resist coatings have little process latitude for current trim etch methods due to the inherently thin resist. In addition, there is no known method for reducing the linewidth of ultra thin resist features without compromising selectivity between the resist and the underlying layer (e.g., device film layer) during the etch operation. Therefore, it would be desirable to have a method for reducing the linewidth of ultra thin resist features without compromising selectivity between the resist and the underlying layer during the etch process. Furthermore, it would be desirable to have such a method that reduces manufacturing costs while improving precision and operating speed.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features formed on a wafer. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 Å formed over a semiconductor structure. The densification process involves an implantation step, wherein the ultra thin resist is implanted with a dopant before being used to etch an underlying layer. The implantation densifies the ultra thin resist and improves etch selectivity of ultra thin resists relative to underlying layers. Following implantation, current or conventional trim (isotropic etching) techniques may be used to further reduce the ultra thin resist linewidth.
The amount of linewidth reduction varies with the degree of densification. The degree of densification may be controlled by implant parameters such as the dopant species, dose, degree of tilt from normal orientation (i.e., incident angle to normal vector of the wafer plane or degree normal to the wafer plane) and energy level employed. Thus, the densification process facilitates controlled linewidth reduction of features formed on ultra thin resist films having a thickness of less than 2500 Å. This improved precision yields increased operating speeds and leads to reduction in manufacturing costs as well.
In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is pattern
Bell Scott
Ng Che-Hoo
Pike Christopher Lee
Sanderfer Anne
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Chen Kin-Chan
LandOfFree
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