Method for tuning an embedded capacitor in a multilayer...

Details Method for tuning an embedded capacitor in a multilayer... Method for tuning an embedded capacitor in a multilayer...

2007-05-22

2007-05-22

Tugbang, A. Dexter (Department: 3729)

Metal working

Barrier layer or semiconductor device making

Barrier layer device making

C029S025410, C029S025420, C029S852000, C029S846000, C029S847000, C257S303000

Reexamination Certificate

active

10653289

ABSTRACT:
Exemplary techniques for tuning the effective capacitance provided by an embedded capacitor are disclosed. The techniques may be realized by modifying one or more conductive features of one or more vias connected to the embedded capacitor to adjust the capacitance contributed by the one or more vias. One technique preferably includes altering the conductive surface area of a pad of one or more vias to which the embedded capacitor is electrically connected to increase or decrease the contributed capacitance. Another technique provides for bore drilling or tap drilling one or more vias connected to the embedded capacitor to increase the surface area of plated interior surfaces of the vias, thereby increasing their capacitive effect. An additional technique includes forming a number of vias having various capacitive effects and electrically connecting the embedded capacitor to one or more of these vias to increase the capacitance.

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Howard Johnson and Martin Graham, “High-Speed Digital Design: A Handbook of Black Magic,” pp. 257-258.

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