Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2003-03-17
2004-05-11
Toledo, Fernando L. (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S381000, C438S383000, C438S638000
Reexamination Certificate
active
06734076
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of thin film resistors and more specifically to a method of forming a thin film resistor in a dual damascene structure with copper interconnects.
BACKGROUND OF THE INVENTION
Thin film resistors are very attractive components for high precision analog and mixed signal applications. In addition to a low thermal coefficient of resistance, low voltage coefficient of resistance, and good resistor matching they should provide good stability under stress.
High frequency mixed signal applications require the use of copper interconnects. Integrated circuit copper interconnects are formed using damascene processes. In a damascene process a trench is first formed in a dielectric layer. The trench is then filled with copper and the excess copper is removed by a number of methods including chemical mechanical polishing.
The formation of thin film resistors in an integrated circuit containing copper interconnects presents many challenges. The thin film resistor is not formed using copper and so is incompatible with existing damascene processes. The incompatibility is exacerbated by the requirement that the thin film resistors be formed in the same levels as the copper interconnects. There is therefore a need for a method to form thin film resistors in integrated circuits with copper interconnects formed using damascene processes.
SUMMARY OF THE INVENTION
The instant invention describes a method for integrating a thin film resistor into an integrated circuit comprising copper interconnects formed using dual damascene structures. In an embodiment of the instant invention an etch stop layer is formed on a dielectric layer. A thin film resistor is formed over the etch stop layer and contact pads are formed on the thin film resistor. A second dielectric layer is formed over the thin film resistor and at least one trench is formed in the second dielectric layer. At the same time thin film resistor vias are formed above the contact pads on the thin film resistor. A via trench is formed in the trench structure and metal is formed in the trench, via trench, and thin film resistor vias.
REFERENCES:
patent: 3988824 (1976-11-01), Bodway
patent: 5976943 (1999-11-01), Manley et al.
patent: 6110772 (2000-08-01), Takada et al.
patent: 6323096 (2001-11-01), Saia et al.
patent: 6500724 (2002-12-01), Zurcher et al.
patent: 6534374 (2003-03-01), Johnson et al.
patent: 6610569 (2003-08-01), Shimamoto et al.
patent: 2002/0132442 (2002-09-01), Roy et al.
Beach Eric W.
Jaiswal Rajneesh
Brady III W. James
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Toledo Fernando L.
LandOfFree
Method for thin film resistor integration in dual damascene... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for thin film resistor integration in dual damascene..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for thin film resistor integration in dual damascene... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3250567