Method for thermal impedance evaluation of packaged semiconducto

Details Method for thermal impedance evaluation of packaged semiconducto Method for thermal impedance evaluation of packaged semiconducto

1996-11-27

1999-07-27

Gutierrez, Diego

Thermal measuring and testing

Determination of inherent thermal property

374 44, G01N 2520, G01N 2518

Patent

active

059278536

ABSTRACT:
A method for evaluating the thermal impedance of packaged semiconductor chips. A measuring apparatus includes a thermostatic bath filled with a dielectric liquid and a temperature sensor for measuring the temperature of the bath. The semiconductor chip is subjected to a calibration step followed by a thermal response measurement step. Increasing the power pulse length allows measurement of the steady-state junction-to-case thermal resistance. The measuring apparatus and method is further used for tracing in-situ degradation of packaged semiconductor chips due to power cycling.

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