Method for the simultaneous manufacture of bipolar and complemen

Details Method for the simultaneous manufacture of bipolar and complemen Method for the simultaneous manufacture of bipolar and complemen

1986-06-02

1988-01-05

Roy, Upendra

Fishing, trapping, and vermin destroying

357 42, 357 43, 437 31, 437 34, 437 44, 437 45, 437189, 437200, H01L 21265, H01L 2122, H01L 2978

Patent

active

047176865

ABSTRACT:
A method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate, wherein n-doped wells are produced in a p-doped substrate for accepting p-channel transistors and npn bipolar transistors are formed into the n-doped wells, the n-well forming the collector of the transistor and the n-wells overlying buried n.sup.+ -doped zones which are connected in the bipolar transistor region by more deeply extending collector plugs. A buried part and plug region of the collector are produced before the production of the wells, and the collector region is formed in the substrate in common with the well so the high-temperature step after the conventional LOCOS process is eliminated. The well implantation is self-adjusting relative to the implantation of the deep collector plug which is annularly formed in the well. A reduction of the collector series resistance as well as an increased latch-up hardness is obtained. Further, the parasitic substrate-pnp is reduced. The method is particularly useful for the manufacture of VLSI circuits with high switching speeds.

REFERENCES:
patent: 4459741 (1984-07-01), Schwabe et al.
patent: 4484388 (1984-11-01), Iwasaki
patent: 4505766 (1985-03-01), Nagumo et al.
patent: 4525920 (1985-07-01), Jacobs et al.
patent: 4536945 (1985-08-01), Gray et al.
patent: 4604790 (1986-12-01), Bonn
patent: 4637125 (1987-01-01), Iwasaki et al.
Momose et al., IEEE-Trans. Electron Devices, ED-32, Feb. 1985, p. 217.
"A 1.0 .mu.m N-Well CMOS/Bipolar Technology for VLSI Circuits" by Miyamoto et al., IEDM Technical Digest (Dec. 1983), pp. 63-66.

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