Method for the simulation of an error in a logic circuit and a c

Details Method for the simulation of an error in a logic circuit and a c Method for the simulation of an error in a logic circuit and a c

1986-04-16

1987-12-22

Atkinson, Charles E.

Excavating

371 25, 364578, G06F 1122, G01R 3128

Patent

active

047150351

ABSTRACT:
A method for the simulation of an error in a logic circuit which comprises a bus optionally connectible to different logic levels, utilizes the assistance of input bit patterns from which output bit patterns are derived via a simulation model containing the error, these output bit patterns being compared to reference bit patterns which are valid for error-free operation. The object is a reliable recognition of an error which leads to a bus conflict, by applying different logic levels to the same circuit mode, by way of an output bit pattern which deviates from a reference bit pattern. This is achieved in that the bus, including the switch elements connecting the levels, is modeled by gate functions, whereby the undefined bus level given simultaneous connection of different logical levels is imaged into a logical "0" by a first bus model version and is imaged into a "1" by a second bus model version. Both bus model versions are respectively utilized in one segment of the simulation method.

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patent: 3780277 (1973-12-01), Armstrong et al.
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patent: 4308616 (1981-12-01), Timoc
patent: 4527249 (1985-07-01), Van Brunt
Z. Barzilai et al., Fault Simulation for Pass Transistor Circuits Using Logic Simulation Machines, IBM Tech. Discl. Bulletin, vol. 27, No. 5, Oct. 1984, pp. 2861-2864.
J. Hlavicka et al., Fault Model for TTL Circuits, Digital Processes, vol. 2, No. 3, Autumn 1976, pp. 169-180.

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