Method for the programming of the memory cells of a memory and a

Static information storage and retrieval – Floating gate – Particular biasing

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365203, 365218, G11C 1700

Patent

active

050220012

ABSTRACT:
The use of charge pumps to supply bit lines, when programming memory cells connected to a bit line, is avoided by pre-charging this bit line simultaneously with the neutralization of the selection of this bit line. Subsequently, the pre-charging potential is uncoupled and the effects of the neutralization are stopped. It is known that this method of action prevents the breakdown of a single programming potential generator, used to supply all the bit lines. This results in a gain in space in the lay-out of the control circuits of the memory cells in the memory plane. This method can be implemented especially in page mode programming for memories where the memory cells have EEPROM-type floating-gate transistors.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 4601020 (1986-07-01), Arakawa et al.

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