Method for the preparation of lead-on-chip assemblies

Details Method for the preparation of lead-on-chip assemblies Method for the preparation of lead-on-chip assemblies

1996-10-03

1999-05-18

Niebling, John

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438123, 257676, H01L21/60

Patent

active

059045000

ABSTRACT:
In accordance with the present invention, alternate lead-on-chip assembly methodologies have been developed which eliminate the use of a three layer film bonded to the leadframe, as currently employed in the art. According to the present invention, a dielectric paste is dispensed directly onto the top surface of the silicon die instead of the thermoplastic tape currently employed in the art. This approach required the development of apparatus and methods which meet the following requirements, e.g., 1) the method (and apparatus employed therefor) must provide comparable units/hour throughput to existing LOC assembly methods, and 2) the method must provide equivalent or superior package reliability when compared with tape bonded LOC packages. The invention method (and apparatus suitable for use therefor) satisfies these needs.

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patent: 5548884 (1996-08-01), Kim

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