Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-09-07
2003-06-03
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S112000
Reexamination Certificate
active
06573781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to an electronic circuit and also to a method for the operation of an electronic circuit that internally or externally transmits information, in which two different voltage levels are generated by two current sources for signalling.
2. Description of the Prior Art
Such an electronic circuit and the method for the operation of the circuit is generally known (for example, in circuits using LVDS=low voltage differential signals or CML=current logic mode).
One disadvantage of this circuit is comprised therein that the dissipated power of such circuits is extremely high and they therefore require involved cooling systems, which usually are larger with respect to weight and space requirements than the circuits themselves.
It is therefore an object of the invention to provide a method and an electronic circuit arrangement that significantly reduces the amount of dissipated power that is generated.
A significant part of the dissipated power given the known circuits, particularly given what are referred to as “high-speed interconnect” connections, arise because an unnecessarily high voltage level is maintained for achieving signal edges that can be detected adequately well given a bit change, even in time segments wherein no bit change occurs, and this high voltage level leads to correspondingly unnecessarly high dissipated currents and a great deal of waste heat.
SUMMARY OF THE INVENTION
In order to avoid these losses, a significantly lower voltage level can be used during times without a bit change, i.e. without generating a detectable signal edge, whereas in case of a bit change the switching is carried out between the high voltage levels.
The present invention provides a method for the operation of an electronic circuit that internally or externally transmits information, whereby at least one first voltage level and one second voltage level are provided, such that the second voltage level is briefly exceeded for the recognition of the signal edge given a change from the first voltage level to the second voltage level and that an approach to the second voltage level subsequently occurs. In other words, the bit change occurs by a change in voltage levels having a greater magnitude, but the maintenance of the voltage after switchingis accomplished by a voltage difference of a lesser magnitude, so that energy is saved.
An advantageous development of this method provides that a further, additional voltage level that is at a distance from the mean value of the voltage levels be allocated to the two voltage levels, this additional voltage levels is initially selected at the switchover time.
Advantageously, the voltage spacing of the two additional voltage levels can thereby be at least two times, preferably three times, preferably four times as great as the voltage spacing of the first voltage level from the second voltage level.
It is also inventively proposed that maintaining current sources are activated for maintaining the voltage levels during normal operation, i.e. without switching activity, and that an additional current source is cut in upon switchover between the voltage levels and then are subsequently disconnected.
The information to be transmitted can be transmitted as a bit sequence, whereby the two voltage levels represent a 0 and a 1.
Another advantage of the present invention is that the information can be transmitted via a “high-speed interconnect” connection, i.e. a connection whose necessary levels during AC operation (=data change) lies clearly above the level for correct recognition of the continuous signal relative to the noise signals. The allowed uncertainty of the voltage edge (=data edge) at the transmission time of the signal is thereby less than 5%, for example 250 ps peak-to-peak given a period duration of 5 ns.
Further advantageous developments of the inventive method provide that the method occurs in an ASIC component or in an interface with current switching (using for example, CML=current mode logic or LVDS=low voltage differential signals).
It is also advantageous when the first level is a high level and the second level is a low level.
Corresponding to the fundamental idea of the invention, the inventor also proposes an electronic circuit, particularly and ASIC, having a plurality of electrical connections for information transmission, whereby two different voltage levels are generated by two current sources for the signaling, to the effect that two further voltage sources are provided that can be briefly cut in for the recognition of the signal edge given a change from a first voltage level to a second voltage level.
An electronic circuit according to the present invention can also contain an edge recognition circuit that is preferably composed of a flipflop and an EXOR (exclusive OR) element.
Further, two through-connect transistors can be provided that connect the data signal through from an input to the output. Just as advantageously, an inverter can be provided or driving a through-connect transistor and a delay element can be allocated to the EXOR element.
Especially advantageously, the inventive electronic circuit can be employed in a “high-speed interconnect” connection.
Another possible use of this electronic circuit is in an interface with current switching (for examplel, CML=current mode logic).
It is self-evident that the aforementioned features of the invention that are yet to be explained below is not limited to the disclosed combination but may also be applied in other combinations or in isolation according to the scope of the invention.
REFERENCES:
patent: 4829199 (1989-05-01), Prater
patent: 5122690 (1992-06-01), Bianchi
patent: 5153450 (1992-10-01), Ruetz
patent: 5166555 (1992-11-01), Kano
patent: 5204558 (1993-04-01), Kumaki et al.
patent: 5959473 (1999-09-01), Sakuragi
patent: 6265892 (2001-07-01), Jou et al.
patent: 38 08 737 (1989-01-01), None
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Zweizig Jeffrey
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