Boots – shoes – and leggings
Patent
1985-12-31
1988-08-09
Gruber, Felix D.
Boots, shoes, and leggings
364200, 371 23, G06F 1520, G06F 1122
Patent
active
047632895
ABSTRACT:
A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.
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Barzilai Zeev
Iyengar Vijay S.
Rosen Barry K.
Silberman Gabriel M.
Gruber Felix D.
International Business Machines - Corporation
Schlemmer Roy R.
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