Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1994-01-25
2001-10-23
Clark, Shelia V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000
Reexamination Certificate
active
06307261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a process for the fabrication of a semiconductor device which includes at least one chip, and to the corresponding device.
2. Discussion of the Background
Known processes for manufacturing semiconductor devices may be classified into three categories:
a) individual processes commonly called “die bonding” for sequential electrical connection by the bonding of metal leads, made of gold or aluminium, between a chip and electrical connection pins.
After making the electrical connections via metal leads, the chip arranged on a support is encapsulated in a plastic, or this support is filled up in order to obtain hermeticity.
However, devices obtained by these industrially reliable processes have the drawback of occupying a large area and a volume more than ten times greater than that of the chip which the device includes;
b) processes of mass-production manufacture using a tape transfer technique (“TAB” or “tape automated bonding”), such as are extensively described in the article “TAB Implementation and Trends”, by Paul HOFFMANN—Mesa Technology, Mountain View, Calif.—pages 85 to 88 of the journal “Solid State Technology” of June 1988.
The tenor of this article is deemed to be incorporated into the present description.
These processes, the productivity of which is greater than that of the individual processes, advantageously allow the chips to be tested before the final assembly, but they have the drawback of requiring a special treatment of the silicon wafers and also of occupying a large area;
c) processes for electrical connection between a chip and connection pins, by the melting of metal microballs: these processes, known by the name of “flip chip” have the drawback of requiring a special treatment of the silicon wafers, and are difficult to implement reliably when the connection support and the chip have different thermal expansion coefficients. Inspection of the corresponding bonded joints is complicated and difficult to carry out.
In addition, the corresponding manufacturing equipments are specific and not widely available; the cost of this type of equipment leads to a high cost of the semiconductor devices fabricated by this process.
SUMMARY OF THE INVENTION
The aim of the invention is to create a new fabrication method capable of being implemented by means of existing manufacturing equipments, so as to produce devices which have a minimum size, which can be easily tested and inspected visually, and which can be inserted into electronic devices where the reduction in size is paramount, like pacemakers, for example.
The object of the invention is a method for the fabrication of a semiconductor device.
According to other features of the invention:
after a step of coating with heat-stable and electrically insulating material and before a metallization step, a V-shaped groove is scribed on an electrically insulating and heat-stable material at a site of tracks for cutting off chips;
the coating with electrically insulating and heat-stable material is performed so as to define pads at the location of the metal leads.
According to other features of the invention:
metallized contacts are located at locations corresponding to projecting pads on a face of the device;
the metallized contacts include a sloping side facilitating visual inspection;
the chip forms the support of the device;
the support of the device is a multilayer circuit which includes metallizations;
the multilayer support is connected to at least one chip, and the support is coated, at least on a side facing the chip, with a thickness of electrically insulating and heat-stable material corresponding to the electrical insulation of the support, the electrically insulating and heat-stable material being penetrated by at least one metal connection lead;
the device includes at least one resistor deposited at an interface between two adjacent layers.
REFERENCES:
patent: 4667219 (1987-05-01), Lee et al.
patent: 4926241 (1990-05-01), Carey
patent: 5065227 (1991-11-01), Frankeny et al.
patent: 5475236 (1995-12-01), Yoshizaki
patent: 0448276 (1991-09-01), None
patent: 2622741 (1989-05-01), None
patent: 2092376 (1982-08-01), None
patent: 810188443 (1983-05-01), None
patent: 8801668 (1988-12-01), None
Campenhout Yves Van
Gilet Dominique
Val Christian
Clark Shelia V.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thomson - CSF
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