Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2002-10-16
2004-07-27
King, Roy (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S126000, C205S196000, C205S205000, C205S208000, C205S220000, C427S098300, C427S259000, C427S282000, C427S304000, C427S305000, C427S404000, C427S443100, C438S382000
Reexamination Certificate
active
06767445
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a process for the manufacture of double-sided or multi-layer printed circuit boards with integral plated resistors. The proposed method selectively activates exposed areas of a metal clad laminate to accept plating thereon in a process for manufacturing printed circuit boards. The method of the instant invention does not use a plating mask so that much smaller areas may be plated onto the printed circuit board. Other advantages are also realized by the process of the instant invention as compared to the prior art.
BACKGROUND OF THE INVENTION
In the manufacture of printed circuits, it is commonplace to provide planar boards having circuitry on each side thereof. It is also commonplace to produce boards comprised of integral planar laminates of insulating substrate and conductive metal, wherein one or more parallel innerlayers or planes of the conductive metal, separated by insulating substrate, are present within the structure with the exposed outer surfaces, along with the inner planes, of the laminate containing printed circuit patterns.
The typical manufacturing sequence for producing printed circuit boards begins with a copper-clad laminate. The copper-clad laminate comprises a glass reinforced epoxy insulating substrate with copper foil adhered to both planar surfaces of the substrate, although other types of insulating substrates such as paper phenolic and polyimide have also been used. In the case of multi-layer boards, the starting material is a copper clad laminate, which comprises inner planes of circuitry called innerlayers.
Simple printed circuit boards and innerlayers of a multi-layer circuit board are generally produced through a technique called print and etch. In this manner, a photopolymer is laminated or coated on the copper surface of a copper clad laminate. The photopolymer is then selectively imaged using negative or positive photomask technology and developed to produce the desired circuit pattern on the surfaces of the copper clad laminate. The exposed copper is then etched away and the photopolymer stripped, revealing the desired circuit pattern.
Embedded passive technology (EPT) is a relatively new technology that has been used to fabricate passives, such as resistors and capacitors, into printed circuit boards during the board fabrication process. Compared with integrated passives, in which passive arrays and networks are arranged on carrier substrates, embedded passives are fabricated into the substrate during processing. EPT is driven by various factors, including the need for better electrical performance, higher packaging density of passives, and potential cost savings. Using EPT, passives may be placed directly below the active device, thus resulting in a shorter distance between the passive and active components and reducing the parasitic effect associated with surface mounted passives, resulting in better signal transmission and less cross talk.
One example of an EPT process is described in U.S. Pat. No. 6,281,090 to Kukanskis et al., the subject matter of which is incorporated herein by reference in its entirety. This process involves the following sequence of processing steps: 1) applying an etch resist on the surface of a metal clad laminate (or multilayer package) in a desired pattern, wherein the pattern preferably defines the conductive circuits desired in a positive manner and defines the areas between the circuits and locations for the resistors in a negative manner; 2) etching away the exposed copper and preferably removing the etch resist; 3) activating the surfaces to accept plating thereon; 4) applying a plating mask which covers substantially all of the surfaces except for the areas where the resistors are to be plated; 5) plating the exposed areas with a resistive material; 6) stripping away the plating mask; and 7) coating the surface of the board with a protective coating.
In contrast, the process of the instant invention does not use a mask during the plating step but instead selectively activates the surface of the metal-clad laminate so as to prevent the entire surface of the substrate from being activated. The selective activation step is generally accomplished using a mask to prevent the entire substrate from being activated. The remaining steps in the process are similar to the process described in the U.S. Pat. No. 6,281,090.
The method of the instant invention provides several key advantages over methods of the prior art.
One notable advantage of the process of the instant invention is that there is no galvanic plating effect caused by the copper cladding. Galvanic effects change the plating potential at the resistor site so that the deposition of the resistive metal will either become less efficient, thereby causing skip plating, or will plate at a greatly reduced thickness, thereby yielding much higher resistor values or a porous plate that will fail under testing. The process of the instant invention solves the problem of galvanic effects by opening up non-essential areas on the copper circuit by removing the plating mask, and causing these areas to plate, thus changing the potential at the resistor site so that uniform plating can be realized. By plating all of the resistors by the novel process of the instant invention, the inventors have discovered that galvanic effects appear to be eliminated.
A second advantage in the process of the instant invention is the ability to plate smaller areas on the printed circuit board because no plating mask is used. The plating mask will create a higher aspect ratio on the three dimensional surface created by the etched copper circuitry, thereby preventing solution access and/or movement into small plating areas. It is generally necessary to use a plating mask to prevent the whole board from plating, which will occur on any activated surface. The process of the instant invention advantageously does not use a plating mask but uses a mask only for selectively activating the surface prior to plating.
The process of the instant invention also realizes greater uniformity and consistency. The inventors have surprisingly observed greater uniformity of resistance for different size resistors.
Finally, the resistive metal used in the process of the instant invention may obviate the need for oxidation of the copper circuitry. Normally, copper circuits used to make a multi-layer core have to be coated with an oxide to reduce the interaction of the copper with the substrate and thereby minimize the likelihood that the multi-layer board will delaminate during the assembly operation. The plating solution of the instant invention provides a barrier layer that does not need further processing to avoid delamination in subsequent processing steps.
SUMMARY OF THE INVENTION
The current invention discloses a process for printing and plating resistors as an integral part of a printed circuit board. The foregoing process is described in its basic form by the following sequence of processing steps:
(a) printing and etching an electronic circuit in a desired pattern on a surface of a metal clad laminate (or multilayer package). The desired pattern should preferably define the conductive circuits desired in a positive manner and should define the areas between the circuits and the locations for the resistors in a negative manner. The laminate will then generally comprise a polymer-based core with metal cladding thereupon in the form of the desired circuit pattern, and openings in said desired pattern of said electronic circuit onto which a resistive material can be plated;
(b) coating said printed and etched electronic circuit (laminate) with a resist so that the openings in the desired pattern and a portion of the metal cladding are exposed;
(c) conditioning and selectively activating the exposed areas of the laminate to accept plating thereon;
(d) stripping the resist; and
(e) plating the activated area with said resistive material to create an integral plated resistor.
In an alternative and preferred embodiment, the printed and etched electronic circui
Durso Frank
Kukanskis Peter
Sawoska David
Carmody & Torrance LLP
King Roy
Leader William T.
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