Method for the manufacture of CMOS FET by P+ maskless technique

Details Method for the manufacture of CMOS FET by P+ maskless technique Method for the manufacture of CMOS FET by P+ maskless technique

1990-08-31

1992-04-21

Hearn, Brian

Fishing, trapping, and vermin destroying

437 28, 437 29, 437 58, 437247, 437979, 148DIG82, 148DIG116, 148DIG163, H01L 21265

Patent

active

051067684

ABSTRACT:
The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.

REFERENCES:
patent: 4474624 (1984-10-01), Matthews
patent: 4480375 (1984-11-01), Cottrell et al.
patent: 4675978 (1987-06-01), Swartz

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