Fishing – trapping – and vermin destroying
Patent
1991-10-02
1993-03-16
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437225, 437228, H01L 21285, H01L 21308
Patent
active
051944030
ABSTRACT:
The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.
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Umebachi et al., "A New Heterojunction Gate GaAs FET", IEEE Transactions on Electron Devices, Aug. 1975, pp. 613-614.
1987 IEEE MTT-S International Microwave Symposium Digest, vol. 2, Jun. 9-11, 1987, pp. 969-972, B. Bayraktaroglu, et al. "AlGaAs/GaAs Heterojunction Bipolar Transistors With 4W/mm Power Density At X-Band".
Collot Philippe
Delage Sylvain
Poisson Marie-Antoinette
"Thomson-CSF"
Chaudhuri Olik
Ojan Ourmazd S.
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