Method for the formation of polycide gate in semiconductor devic

Details Method for the formation of polycide gate in semiconductor devic Method for the formation of polycide gate in semiconductor devic

1995-11-29

1998-01-27

Fourson, George R.

Fishing, trapping, and vermin destroying

437 40, 437200, 437 41, H01L 21265

Patent

active

057121818

ABSTRACT:
A method for the formation of gate in a semiconductor device is disclosed. The method for the formation of gate in a semiconductor device, comprising the steps of: forming amorphous silicon and polysilicon over a gate insulating film atop a semiconductor substrate, in due order; implanting impurity ions into the polysilicon and carrying out heat treatment; and forming a layer of a refractory metal over the silicon and carrying out heat treatment, to form polycide. Capable of preventing the degradation which is attributed to the penetration of impurities and thermal instability when forming a P.sup.+ polygate, the method contribute to the improvement in electrical properties.

REFERENCES:
patent: 4950617 (1990-08-01), Kumagai et al.
patent: 4978629 (1990-12-01), Komori et al.
patent: 5030584 (1991-07-01), Nakata
patent: 5081066 (1992-01-01), Kim
patent: 5147820 (1992-09-01), Chittipeddi et al.
patent: 5185279 (1993-02-01), Ushiku
patent: 5278096 (1994-01-01), Lee et al.
patent: 5279976 (1994-01-01), Haden et al.
patent: 5298436 (1994-03-01), Radosevich et al.
patent: 5321286 (1994-06-01), Koyama et al.
patent: 5330929 (1994-07-01), Pfiester et al.
patent: 5350698 (1994-09-01), Huang et al.
patent: 5364803 (1994-11-01), Lur et al.
patent: 5393682 (1995-02-01), Liu
patent: 5393687 (1995-02-01), Liang
patent: 5438006 (1995-08-01), Chang et al.
patent: 5441904 (1995-08-01), Kim et al.
Article Entitled "Junction Leakage Due to CoSI.sub.2 Formation on As-Doped Polysilicon" by J.P. Gambino and B. Cunningham, Published Sep. 1993 in J. Electrochem. Soc., vol. 140, pp. 2654-2658.
Article Entitled "High-Temperature Effects on a Co-SI.sub.2 /Poly-SI Metal Oxide Semiconductor Gate Configuration" by Stefan Nygren and Stefan Johansson, Published May/Jun. 1990 in J. Vac. Sci. Technol. A8(3), pp. 3011-3013.

Affiliated with

Also associated with

Rating

Method for the formation of polycide gate in semiconductor devic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for the formation of polycide gate in semiconductor devic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the formation of polycide gate in semiconductor devic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-341775