Method for the erasure of a memory, and circuits for the impleme

Details Method for the erasure of a memory, and circuits for the impleme Method for the erasure of a memory, and circuits for the impleme

1995-04-12

1997-04-08

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518511, G11C 1134

Patent

active

056194510

ABSTRACT:
A method for erasing a non-volatile electrically erasable and programmable integrated circuit memory that is divided into N sectors selected separately by addressing circuits and the cells for each sector being selected by row and column addressing circuits wherein an erasure pulse is applied simultaneously to all the sectors. The checking of the erasure of each sector leads to the locking of the sector when no defect is detected. A new erasure pulse is applied only to the unlocked sectors and only the unlocked sectors are rechecked. Also, a circuit for locking sectors in order to implement the method is disclosed.

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French Search Report from French application 94 04393.
IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, New York US pp. 1600-1605 Nakayama et al. "A 60ns 16Mb Flash EEPROM With Program and Erase Sequence Controller".

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