Method for testing word line leakage in a semiconductor memory d

Details Method for testing word line leakage in a semiconductor memory d Method for testing word line leakage in a semiconductor memory d

1996-09-19

1998-12-01

Nguyen, Hoa T.

Excavating

371 214, G11C 2900

Patent

active

058449159

ABSTRACT:
A word line leak check test for a semiconductor memory arranged as a matrix which includes word lines and y-selection lines. First, a RAS signal is enabled while a prescribed row address is input, and word line 22 is driven to the Vpp level. Then, when the CAS signal is enabled, the voltage source is disconnected from word line 22, and word line 22 floats. Two bits for the column address are disregarded, and the Y selection signal line 23 is decoded without those 2 bits. By this means, 4 y-selection signal lines 23 are simultaneously enabled. When this condition has been maintained for a prescribed time T, a delayed write operation is conducted, and then it is determined whether the data has been correctly stored in memory cell 24.

REFERENCES:
patent: 4004222 (1977-01-01), Gebhard
patent: 4896322 (1990-01-01), Kraus et al.
patent: 5117426 (1992-05-01), McAdams
patent: 5610867 (1997-03-01), DeBrosse et al.

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