Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-03-13
2003-01-14
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S118000, C702S035000
Reexamination Certificate
active
06507800
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor processing, and more particularly, to an improved method of classifying semiconductor wafers according to particular characteristics.
BACKGROUND OF THE INVENTION
Semiconductor wafer fabrication involves complex manufacturing processes to produce integrated circuits on the surface of silicon wafers. To ensure the quality of the integrated circuit chips, various testing methods have been devised to find defects on the wafer in order to improve the manufacturing processes. One method is to place testing circuitry at various locations on the wafer, and use test signals to determine the functionality of the circuitry. The resulting test data is then used to generate defect patterns. Typically, an experienced engineer then analyzes the defect patterns and determines the root cause of the defects. For example, a defect pattern having curvilinear features may resemble a mechanical scratch; the grouping of low-density, sparse structures into amorphous clusters might resemble the trail off of a teardrop shaped stain.
During the initial run of a semiconductor wafer production line, electrical testing is conducted on each wafer manufactured, and the defect patterns of the wafer are used to produce a set of standard defect wafer maps. Each defect wafer map corresponds to a particular kind of defect pattern, and different defect wafer maps may be linked to different problems in the manufacturing process. After the set of standard defect wafer maps are generated, the defect pattern obtained from a subsequently manufactured wafer can be compared against the standard defect wafer maps to determine the cause of the defects.
Manually comparing the defect patterns with the standard defect wafer maps can be a tedious and time-consuming work. As the number of wafers manufactured is increased, it is feasible to have an automated process for performing the pattern recognition. However, when there is more than one defect in the manufacturing process, the defect patterns caused by the various defective processes may overlap, producing an obscured defect pattern. This may result in incorrect determination of the cause of the defect, lengthening the time required to perfect the manufacturing process.
The present invention is directed to an improved method for failure mode classification of semiconductor wafers using discriminant analysis and cluster analysis.
SUMMARY OF THE INVENTION
A method for identifying failure signatures of semiconductor wafers is disclosed. The method includes the steps of providing a number of wafers having circuit patterns; testing each of the wafers to obtain a first set of test data, the first set of test data including a first subset of test data obtained from wafers associated with a failure signature and a second subset of test data obtained from wafers not associated with the failure signature; generating coefficients for a discriminant function; performing tests on a subsequently manufactured wafer to obtain a second set of test data, applying the discriminant function to the second set of test data to obtain a discriminant value, and identifying the subsequently manufactured wafer as having the failure signature when the discriminant value is greater than or equal to a threshold value.
REFERENCES:
patent: 5450326 (1995-09-01), Black
patent: 5991699 (1999-11-01), Kulkarni et al.
patent: 6289292 (2001-09-01), Charlton et al.
patent: 6336086 (2002-01-01), Perez et al.
Blakely & Sokoloff, Taylor & Zafman
Promos Technologies Inc.
Wachsman Hal
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