Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
2001-12-10
2003-02-11
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Repair or restoration
C438S012000, C438S018000
Reexamination Certificate
active
06518073
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority to Japanese Patent Application No. 8-11029, filed Jan. 25, 1996, which is incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method for testing a semiconductor memory which uses redundancy technology, and also to an apparatus designed to test that memory.
Most of the semiconductor devices manufactured at the present time adopt redundancy technology. The adoption of this technology is intended to increase the number of good products manufactured. The redundancy technology is directed to a technique for replacing defective memory cells or defective rows/columns of a main cell array with spare rows/columns. The redundancy technology is useful in remedying defective semiconductor devices, and therefore contributes to an increase in the manufacturing yield of semiconductor memories.
A test for testing a semiconductor device which uses redundancy technology includes three testing items, namely, a DC characteristic test, a function (FNC) test, and redundancy (R/D) analysis. The DC characteristic test is a test for checking the DC characteristic of a semiconductor memory. The FNC test is a test for checking the functions of the semiconductor memory. In the R/D analysis, the location of a defective portion of a main memory cell array is checked on the basis of the results of the FNC test, and an arithmetic operation for replacing the memory cell and row/column at the defective portion with a spare row/column is executed on the basis of the replacement program.
FIG. 1
is a block circuit diagram showing a conventional semiconductor memory tester.
Referring to
FIG. 1
, the memory tester comprises a memory testing unit
100
, an operation terminal
101
for operating the memory testing unit
100
, and a test station
150
where a wafer is placed for test. The memory testing unit
100
includes a CPU
102
, a main memory
103
which stores a test program (TEST PRG.) and OS, and further stores a replacement program (R/D PRG) used in the arithmetic operation for replacement, a DC characteristic/function tester which outputs test patterns (
1
) and (
2
) and an expected value (
3
), a determination device
105
which compares the expected value (
3
) with a response signal (
4
) supplied from a DUT (not shown), determines whether or not the response signal represents a normal state, and supplies determination information (
5
) to the CPU
102
, and a fail memory
107
which stores information (
6
) regarding the occurrence of an abnormal state when abnormality is detected with respect to the DUT. In
FIG. 1
, reference numeral (
9
) denotes control information issued by CPU
102
.
The memory tester mentioned above executes a DC characteristic test and an FNC test with respect to the DUT in accordance with the test program. If an abnormal state is detected with respect to the DUT in the test, the information (
6
) regarding the occurrence of the abnormal state is stored in the fail memory
107
.
After the DC characteristic test and the FNC test, the R/D analysis is executed on the basis of the test program. In this analysis, information (
7
) representing the location of a defective portion of the main memory cell array is extracted from information (
6
) and read out from the fail memory
107
. An operation unit (not shown), included in the CPU
102
, analyzes the readout information (
7
) in accordance with the replacement program and carries out the operation for replacing the defective portion with a spare row/column. Results of this replacement operation (i.e., replacement information RPLC DATA) are used in the redundancy step to check which fuse should be blown by a laser blower. The results of the replacement operation are stored in a storing medium, such as a floppy disk, by means of the operation terminal
101
.
The memory tester shown in
FIG. 1
serially executes the DC characteristic test, the FNC test, and the R/D analysis. The reason for the serial execution is that the operations described in the test program are executed by a single CPU (CPU
102
).
An increase in the memory capacity entails an increase in the number of memory cells, and results in miniaturization of memory cells. In addition, since the internal wiring is of a multi-level structure, the manufacturing process is complicated, accordingly. As shown in
FIG. 2
, the number of defective memory cells increases in accordance with an increase in the memory capacity. In order to reliably remedy the defective memory cells, the number of spare rows/columns is also increasing, as shown in FIG.
3
.
An increase in the memory capacity entails not only an increase in the number of memory cells but also an increase in the number of peripheral circuits, such as row/column decoders. Accordingly, the time needed for testing one DUT is inevitably long.
FIG. 4
shows the relationships between the total test time for one DUT and the memory capacity.
FIG. 5
shows the relationships between the total test time for one wafer and the memory capacity. In preparing the data shown in
FIG. 5
, it was assumed that the total test time for one wafer was equal to the total length of time of the test times for four DUTs. (In actuality, 80 to 130 DUTs correspond to one wafer. Since all DUTs cannot be depicted, they are compressed into four DUTs, for simplicity.)
As shown in
FIG. 4
, an increase in the test time for one DUT does not become a problem when the memory capacity changes from “1MDRAM” to “4MDRAM”. However, when the memory capacity changes from “4MDRAM” to “16MDRAM”, the total test time poses a poor throughput problem since it is about twice as long as the total test time of the case of “1MDRAM”. To solve this problem, a technique referred to as “multi-probing” is employed to shorten the total test time. The “multi-probing” is specifically a method in which a plurality of DUTs are tested at one time. In
FIG. 5
, the data corresponding to “16MDRAM” is data obtained when two DUTs are tested at one time. In comparison with the case of “single-probing” (indicated by line I in
FIG. 5
) where DUTs are tested one by one, the use of the “multi-probing” technique is advantageous in that the total test time required is half. The use of the “multi-probing” technique is advantageous to a certain degree when the memory capacity changes from “16MDRAM” to “64MDRAM”. However, when the memory capacity advances to “256MDRAM”, the total test time is about twice as long as that of the case of “16MDRAM”, as indicated by line II. This being so, it is generally thought that the “expansion of multi-probing” is tried when 256MDRAMs are mass-produced. The “expansion of multi-probing” is to increase the number of DUTs tested at one time. For example, the number of DUTs tested at one time is increased from “32” to “64”. The use of the “expansion of multi-probing” shortens the total test time.
The ultimate purpose of the multi-probing is to test all DUTs on a wafer. However, in the cases where the memory capacity is greater than “256MDRAM”, there are no DUTs that can be tested at one time, as shown in FIG.
5
. In such cases, a decrease in the total test time required for one wafer does not result in any advantage. The total test time for one wafer increases, depending upon the total test time for one DUT.
After the expansion of multi-probing does not produce any advantage, the technique which is available for improving the throughput is merely to increase the number of memory testers employed, thereby enhancing the throughput of the production lines system per unit time.
However, the adoption of this technique is disadvantageous in that a large number of costly memory testers are newly required and that the existing production lines have to be modified or new production lines have to be installed. Such facility investment greatly increases the manufacturing cost of one semiconductor memory device.
In recent years, a new testing method is proposed wherein the DC characteristic test and FNC test for a DUT are executed independently of
Chaudhari Chandra
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
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