Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1995-12-29
1998-09-29
Karlsen, Ernest F.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324758, G01R 3102
Patent
active
058150005
ABSTRACT:
A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
REFERENCES:
patent: 4169642 (1979-10-01), Mouissie
patent: 4597617 (1986-07-01), Enochs
patent: 4783719 (1988-11-01), Jamison et al.
patent: 4899921 (1990-02-01), Bendat et al.
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5073117 (1991-12-01), Malhi et al.
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5367253 (1994-11-01), Wood et al.
patent: 5397245 (1995-03-01), Roebuck et al.
patent: 5408190 (1995-04-01), Wood et al.
patent: 5419807 (1995-05-01), Akram et al.
patent: 5451165 (1995-09-01), Cearley-Cabbiness et al.
patent: 5456404 (1995-10-01), Robinette, Jr. et al.
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495179 (1996-02-01), Wood et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5530376 (1996-06-01), Lim et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
Nakano, M.; Disclosure No. HEI 3-69131; J-Tech Translations, 24 Pear Tree Lane, Terre Haute, IN 47803; no date; (This is a translation of unexamined Japanese Patent Application No. 3-69131 published Mar. 25, 1991.).
Akram Salman
Farnworth Warren M.
Hembree David R.
Wood Alan G.
Gratton Stephen A.
Karlsen Ernest F.
Micro)n Technology, Inc.
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