Method for testing overlay in a semiconductor device utilizing i

Radiation imagery chemistry: process – composition – or product th – Registration or layout process other than color proofing

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430 30, 356399, G03F 900

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active

057668094

ABSTRACT:
A method for testing an overlay occurring in a semiconductor device to compensate for an error generated in the measurement of overlay. This method involves forming an inner mark on a semiconductor wafer, and forming an outer mark on the semiconductor wafer in such a fashion that the outer mark is inclined in one direction and has an island portion arranged in the inside of the inner mark and a land portion comprised of a photoresist film pattern formed over the entire surface of the semiconductor wafer while being spaced from the island portion by a desired distance, thereby forming an overlay measuring mark consisting of the inner and outer marks. Measured values of the island and land portions of the inner mark are averaged and then compared with measured values of the outer mark, thereby deriving overlay compensation values. Accordingly, even if the overlay measuring mark is formed in an inclined state, the method can simply measure an inaccuracy in measured overlay value. Even when the overlay correction value varies subsequently due to a variation in conditions of the overlay measuring device or process, an accurate overlay correction value can be derived by conducting the overlay measuring process only once. The overlay margin in the overlay test can increase, thereby achieving an improvement in process yield and operation reliability.

REFERENCES:
patent: 5280437 (1994-01-01), Corliss
patent: 5438413 (1995-08-01), Mazor et al.
patent: 5498500 (1996-03-01), Bae
patent: 5635336 (1997-06-01), Bae

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