Method for testing non-volatile memories

Details Method for testing non-volatile memories Method for testing non-volatile memories

1992-09-25

1995-01-17

Beausoliel, Jr., Robert W.

Excavating

365201, G11C 2900

Patent

active

053831934

ABSTRACT:
A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications. In suitably equipped memories, the addresses of weak cells can be recorded and redundant cell groups substituted as replacements.

REFERENCES:
patent: 4573146 (1986-02-01), Graham et al.
patent: 4639897 (1987-01-01), Wacyk
patent: 4920515 (1990-04-01), Obata
patent: 5031152 (1991-07-01), Doyle

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