Method for testing leakage current caused self-aligned silicide

Details Method for testing leakage current caused self-aligned silicide Method for testing leakage current caused self-aligned silicide

1999-11-23

2001-06-19

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S719000, C438S014000, C438S017000

Reexamination Certificate

active

06249138

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for testing reliability of a self-aligned silicide process. More particularly, the present invention relates to a method for testing a leakage current caused by self-aligned silicide, using different test structures after a self-aligned silicide process.
2. Description of Related Art
In a conventional method for testing reliability of a self-aligned silicide process, test structures, as shown in FIG.
1
and
FIG. 2
, are commonly deposited on wafer scribe lines. These test structures include a big diffusion region
102
(FIG.
1
), or multiple bars of diffusion regions
102
on the wafer
100
(FIG.
2
), and a metal silicide layer
104
thereon. These test structures and a metal-oxide semiconductor (MOS) transistor in a chip are simultaneously formed, therefore, the test structures can monitor reliability of the self-aligned silicide layer on a source/drain region of the MOS transistor to avoid malfunction of the MOS transistor. The two test structures (shown in FIG.
1
and
FIG. 2
) are designed according to a leakage current occurring from the metal silicide layer to the junction, and a leakage current occurring at the edge of the metal silicide layer. Therefore, design parameters of the two test structures in
FIGS. 1 and 2
include area and perimeter of the metal silicide layer.
Accordingly, the conventional method for testing reliability of a self-aligned silicide process is to measure a current of the test structure shown in
FIG. 1
or
FIG. 2
, and then calculate current density from the metal silicide to the junction region and current density of the edge of the metal silicide. According to these two current densities, the leakage current caused by the metal silicide layer can be monitored. If the leakage current is not in an allowable range, the self-aligned silicide process has to be immediately rectified so as to reduce wafer nullity probability.
However, when the test structures shown in
FIG. 1 and 2
are employed in 0.25 &mgr;m semiconductor processes, some problems arise. The device malfunction probability is still large when testing for device electricity after the whole semiconductor processes, even though the test result of the self-aligned process is favorable. In other words, the conventional test structure cannot accurately monitor the reliability of the self-aligned process. This leads to an increase of the wafer malfunction probability and capital expenditure.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method for testing reliability of a self-aligned silicide process. The method can be employed in a 0.25 &mgr;m or lower than 0.25 &mgr;m semiconductor process.
The invention provides a method for testing reliability of a self-aligned silicide process. The invention uses different test structures to monitor degree of and reason for a current leakage caused by a self-aligned silicide process so as to immediately discover problems, and then immediately resolve the problems.
The invention provides a method for testing reliability of a self-aligned silicide process. In addition to considering a leakage current occurring from a metal silicide layer to the junction and a leakage current occurring at edge of the metal silicide layer, the invention further considers a leakage current occurring from the metal silicide layer to a LDD region and a leakage current occurring at comer of the metal silicide layer adjacent to a shallow trench isolation structure.
Accordingly, the invention provides a method of testing a leakage current caused by a self-aligned silicide process, which is suitable for monitoring the self-aligned silicide process performed on a metal-oxide semiconductor transistor having no lightly doped drain (LDD) structure. At first, parameters for monitoring the self-aligned silicide process are considered. The parameters include an area current density (J
A
) an edge current density (J
E
), and a comer current density (J
C
) A total current (J) of the metal silicide layer is calculated as follows:
J=J
A
×A+J
E
×L+J
C
×C,
wherein A is an area of the metal silicide layer, L is an edge perimeter of the metal silicide layer, and C is comer number of the metal silicide layer. At least three test structures including a first test structure, a second test structure, and a third test structure are deposited on a wafer. The first test structure, the second test structure and the third test structure respectively comprises a first, a second and a third diffusion regions and a first, a second, and a third metal silicide layer on the first, the second, the third diffusion regions. The first, the second and the third diffusion regions are respectively surrounded by a first, a second, and a third isolation structures, wherein an area of the first metal silicide layer of the first test structure is A
1
, its edge perimeter is L
1
, its comer number is C
1
, an area of the second metal silicide layer of the second test structure is A
2
, its edge perimeter is L
2
, its corner number is C
2
, and an area of the third metal silicide layer of the third test structure is A
3
, its edge perimeter is L
3
, and its corner number is C
3
. Electricity of the first test structure, the second test structure, and the third test structure is measured to respectively obtain total currents J
1
, J
2
, and J
3
; J
1
, J
2
, and J
3
are then substituted into a total current equation to obtain three linear equations:
J
1
=J
A
×A
1
+J
E
×L
1
+J
C
×C
1
,
J
2
=J
A
×A
2
+J
E
×L
2
+J
C
×C
2
, and
J
3
=J
A
×A
3
+J
E
×L
3
+J
C
×C
3
.
The three linear equations are calculated to obtain a set of values for J
A
, J
E
, and J
C
. The self-aligned silicide process is monitored according to the set of values for J
A
, J
E
, and J
C
.
The invention provides another method of testing a leakage current caused by a self-aligned silicide process, which is suitable for monitoring the self-aligned silicide process performed on a metal-oxide semiconductor transistor having a lightly doped drain (LDD) structure. At first, parameters for monitoring the self-aligned silicide process are considered. The parameters comprises an area current density (J
A
), an interface current density (J
isolation,L
) between the metal silicide layer and a device isolation structure, and a current density (J
LDD,L
) from the metal silicide layer to the LDD region. A total current (J) of the metal silicide layer is calculated as follows:
J=J
A
×A+J
isolation,L
×L
isolation
+J
LDD,L
×L
LDD
,
wherein A is an area of the metal silicide layer, L
isolation
is an interface perimeter between the metal silicide layer and the device isolation structure, and L
LDD
is a path of the LDD region. At least three test structures including a first test structure, a second test structure, and a third test structure are deposited on a wafer. The first test structure, the second test structure and the third test structure respectively comprises a first, a second and a third diffusion regions and a first, a second, and a third metal silicide layers respectively on the first, the second, and the third diffusion regions. The first, the second and the third diffusion regions are electrically isolated by a first, a second, and a third isolation structures. At least one of the first, the second, the third diffusion regions has the LDD region, such that an area of the first metal silicide layer of the first test structure is A
1
, an interface perimeter between the first metal silicide layer and the first device isolation structure is L
isolation1
, a length of the LDD region is L
LDD1
, an area of the second metal silicide layer of the second test structure is A
2
, an interface perimeter between the second metal silicide layer and the second device isolation structure is L
isolation2
, a length of the LDD region is L
LDD2
, an area of the third metal silicide layer

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