Method for testing interconnections between integrated circuits

Details Method for testing interconnections between integrated circuits Method for testing interconnections between integrated circuits

1997-01-17

1998-05-26

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057578206

ABSTRACT:
Methods for testing interconnections on an electronic assembly include the steps of dynamically generating an interconnect topology model from one system, generating test patterns to test the interconnections, applying the test patterns to the boundary scan cells of the system under test to test the interconnections, and determining whether the interconnections match the interconnect topology model. The invention thus dynamically generates an interconnect topology model from a known working system, rather than deriving the interconnect topology model from design data that describes all the interconnections on an electronic assembly.

REFERENCES:
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 5206862 (1993-04-01), Chandra et al.
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5282271 (1994-01-01), Hsieh et al.
patent: 5396170 (1995-03-01), D'Souza et al.
patent: 5410551 (1995-04-01), Edwards et al.
patent: 5475694 (1995-12-01), Ivanov et al.

Affiliated with

Also associated with

Rating

Method for testing interconnections between integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for testing interconnections between integrated circuits , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing interconnections between integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1972370